ESP32S3 Walter Module Development Board Pinout and Technical Specifications
Code name: ESP32S3_DEV
Manufacturer: QuickSpot
ESP32S3 Walter Module development board is based on esp32s3 microcontroller and uses xtensa architecture. This development board has a maximum CPU frequency of 240 MHz and a flash size of 16MB.
π ESP32S3 Walter Module Description
Walter is a small, highly integrated IoT module built to tackle complex connectivity and processing needs. At its core is the ESP32-S3
, a versatile system-on-chip (SoC) featuring a dual-core processor with hardware acceleration for machine learning, cryptography, and signal processing. It includes a range of peripherals, such as UART
, SPI
, IΒ²C
, and CAN
, alongside built-in Wi-Fi b/g/n and Bluetooth 5, providing robust local networking and communication options.
What sets Walter apart is its inclusion of the Sequans GM02SP
modem, offering LTE-M and NB-IoT 5G connectivity for low-power, wide-area communication, ideal for IoT applications. The modem also integrates a GNSS receiver, adding precise positioning capabilities for tasks like asset tracking, navigation, or geolocation.
π ESP32S3 Walter Module Specs
Below you can find the specifications of ESP32S3 Walter Module, such as features, connectivity options, and ESP32S3 Walter Module technical specs.
β¨ Features
- LTE: CAT M1/NB1/NB2 (GM02SP module)
- GPS: GPS, GNSS Constellation support (GM02SP module)
- Ultra low deep sleep current of 9.8Β΅A
- Certified for CE, FCC, IC, UKCA, New-Zealand and Australia
- 24 digital IO pins
- 22 external interrupt pins
- 22 analog input pins
- 22 PWM pins
π°οΈ Connectivity
- WiFi: 802.11 b/g/n (2.4 GHz)
- Bluetooth: 5.0
- BLE: 5.0
- LTE: CAT M1/NB1/NB2
π Technical specs
Microcontroller | esp32s3 |
Clock Speed | 240 MHz |
Flash size | 16MB |
Architecture | xtensa |
β οΈ Pins to Avoid or Use with Caution
Some pins are reserved for critical functions like bootstrapping, JTAG debugging, USB communication, and flash memory operations. Misusing these pins may lead to boot failures, programming issues, USB conflicts, or disruptions in flash storage. Below is a list of pins to avoid or use with caution, categorized for clarity:
- π οΈ Strapping Pins (Boot Mode & System Behavior) - These pins control boot behavior and flash voltage selection. Pulling them high or low at reset can impact boot mode selection, voltage settings, or debugging access. Avoid altering their state unless necessary.
- π JTAG Debugging Pins - JTAG is used for low-level debugging and programming. If JTAG is enabled, these pins must remain dedicated to it. Repurposing them as GPIO can disable JTAG debugging features.
- π USB Communication Pins - These pins are used for USB Serial/JTAG communication. If USB debugging or communication is required, they should not be reassigned as GPIO.
- β‘ Flash Memory & SPI Pins - Certain GPIOs are hardwired to SPI flash memory and PSRAM. Using them as standard GPIOs may result in system instability, corrupted storage, or boot failure.
- π‘ UART Serial Communication Pins - By default, these pins are used for serial debugging, console output, and firmware uploads. Repurposing them for general I/O may break UART programming or debugging capabilities.
PIN | Label | Reason | Function |
---|---|---|---|
IO12 | FSPICLK | Drives the flash (and PSRAM) clock. This critical signal must be reserved for memory and not used as general GPIO. | β‘ Flash |
IO11 | FSPID | Used as a data line for flash (and in-package PSRAM). It should not be used as GPIO when the flash/PSRAM is in use. | β‘ Flash |
IO13 | FSPIQ | Used as a data line for flash/PSRAM transfers. Not available for other uses when flash/PSRAM is connected. | β‘ Flash |
IO38 | FSPIWP | On flash-equipped chips, this pin is tied to the flashβs WP# (or D3) line. It should be avoided for other use, as itβs needed for flash operations. | β‘ Flash |
IO39 | MTCK (GPIO39) | Default JTAG debugging TCK pin. If JTAG is needed, this pin must be free; it may also be used internally for PSRAM chip select on certain modules, so avoid repurposing it. | πͺ Other |
IO40 | MTDO (GPIO40) | Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality. | πͺ Other |
IO41 | MTDI (GPIO41) | Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available. | πͺ Other |
IO42 | MTMS (GPIO42) | Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB). | πͺ Other |
IO9 | FSPIHD | Connected to external flash (data/hold signal) on most modules. Not recommended for use as GPIO, since it must remain dedicated to flash communication. | β‘ Flash |
IO10 | FSPICS0 | Used to select the external flash chip. It is required for flash access and cannot be repurposed without losing flash connectivity | β‘ Flash |
π Key Takeaway:
- Before using any GPIO, check if it is assigned a critical function.
- Avoid using bootstrapping pins unless you're modifying boot behavior intentionally.
- If JTAG debugging is needed, ensure its pins remain free.
- USB and Flash-related GPIOs should remain dedicated unless you disable their default functions.
β Pins Safe to use
- πΉ RESET
- πΉ IO44/RX0
- πΉ IO43/TX0
- πΉ DFU/3V3 EN
- πΉ IO2
- πΉ IO1
- πΉ IO4
- πΉ IO5
- πΉ IO6
- πΉ IO7
- πΉ IO15
- πΉ IO16
- πΉ IO17
- πΉ IO18
- πΉ IO8
- πΉ 3V3 OUT
- πΉ VIN
Unlike restricted pins, these GPIOs are not tied to essential system functions like π οΈ bootstrapping, π USB communication, π JTAG debugging, or β‘ SPI flash memory, making them the best choices for custom applications and general use.
Why Are These Pins Safe?- Not involved in bootstrapping β These GPIOs do not affect the deviceβs boot mode or system startup.
- Not linked to flash memory or PSRAM β They wonβt interfere with storage or memory access.
- Not dedicated to USB or JTAG β They remain free for general use without affecting debugging or programming.
- No special hardware connections β Unlike some pins that are internally wired to system functions, these remain freely assignable.
πΊοΈ ESP32S3 Walter Module External Pins Mapping Functions
Below you can find the ESP32S3 Walter Module pinout. This development board provides 24 digital IO pins, out of which 22 can be used as an external interrupt pins , 22 as analog input pins and 22 pins have Pulse-Width Modulation (PWM) .
Pin | Function | ESP Pin | Input/Output | Description |
---|---|---|---|---|
1 | RESET | EN | input | ESP32 reset with 10k pullup |
2 | IO44/RX0 | RXD0 | bidirectional | ESP32 UART0 Receive |
3 | IO43/TX0 | TXD0 | bidirectional | ESP32 UART0 Transmit |
4 | DFU/3V3 EN | IO0 | bidirectional | DFU when low on boot and 3V3 output enable |
5 | IO12 | IO12 | bidirectional | General purpose I/O |
6 | IO11 | IO11 | bidirectional | General purpose I/O |
7 | IO13 | IO13 | bidirectional | General purpose I/O |
8 | IO38 | IO38 | bidirectional | General purpose I/O |
9 | IO39 | IO39 | bidirectional | General purpose I/O |
10 | IO40 | IO40 | bidirectional | General purpose I/O |
11 | IO41 | IO41 | bidirectional | General purpose I/O |
12 | IO42 | IO42 | bidirectional | General purpose I/O |
13 | IO2 | IO2 | bidirectional | General purpose I/O |
14 | IO1 | IO1 | bidirectional | General purpose I/O |
15 | IO4 | IO4 | bidirectional | General purpose I/O |
16 | IO5 | IO5 | bidirectional | General purpose I/O |
17 | IO6 | IO6 | bidirectional | General purpose I/O |
18 | IO7 | IO7 | bidirectional | General purpose I/O |
19 | IO15 | IO15 | bidirectional | General purpose I/O |
20 | IO16 | IO16 | bidirectional | General purpose I/O |
21 | IO17 | IO17 | bidirectional | General purpose I/O |
22 | IO18 | IO18 | bidirectional | General purpose I/O |
23 | IO8 | IO8 | bidirectional | General purpose I/O |
24 | IO9 | IO9 | bidirectional | General purpose I/O |
25 | IO10 | IO10 | bidirectional | General purpose I/O |
26 | 3V3 OUT | N/A | power output | Switchable 3.3VDC output |
27 | GND | GND | power ground | GND connection |
28 | VIN | N/A | power input | DC Power input port |
π οΈ Default Tools
Bootloader tool | esptool_py |
Uploader tool | esptool_py |
Network uploader tool | esp_ota |
Bootloader address | 0x0 |
Flash mode | dio |
Boot mode | qio |
PSRAM type | qspi |
The ESP32S3 Walter Module development board by default uses esptool_py uploader tool, esp_ota network uploader tool for Over-the-air (OTA) uploads and esptool_py bootloader tool. The bootloader starts at address "0x0". Flash mode and boot mode for ESP32S3 Walter Module development board by default is dio and qio respectively. The board uses qspi PSRAM type.