ESP32-S3 Development Boards
The ESP32-S3 combines Wi-Fi + BLE with AI acceleration via its vector instructions. It is perfect for projects requiring face recognition, gesture detection, or machine learning inference at the edge.
It features a dual-core processor, USB OTG, and enhanced GPIOs supporting 8-bit parallel LCDs and camera interfaces. It’s supported by both ESP-IDF and Arduino, ideal for AIoT development.
Dual-core
Xtensa cores
240 MHz
Max clock
512 KB
SRAM
84
Boards
Specifications
Datasheet ↗Compute
CPUXtensa dual-core 32-bit LX7
Clock240 MHz
SRAM512 KB
Operating temp-40 to 85 °C
Connectivity
Wi-Fi802.11 b/g/n (2.4 GHz)
Bluetooth5.0
BLE5.0
Peripherals
ADCTwo 12-bit, 20 Channels
SPI2
I²C2
I²S2
RMT8 Channels
Touch14
UART3
PWM8
Strapping & reserved pins
32 pins to knowSome pins are reserved for boot strapping, JTAG, USB and flash - misusing them can cause boot failures or programming issues. The category colours below match the table.
Strapping boot mode & flash voltage JTAG low-level debugging USB native USB Serial/JTAG Flash / SPI flash & PSRAM lines PSRAM memory line only on PSRAM-equipped modules UART debug & firmware upload
| Pin | Label | Why avoid | Category |
|---|---|---|---|
| IO0 | GPIO0 | Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration. | Strapping |
| IO3 | GPIO3 | Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface. | Strapping |
| IO9 | FSPIHD | IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI. | Other |
| IO10 | FSPICS0 | IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI. | Other |
| IO11 | FSPID | IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI. | Other |
| IO12 | FSPICLK | IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI. | Other |
| IO13 | FSPIQ | IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI. | Other |
| IO14 | FSPIWP | IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI. | Other |
| IO19 | USB_D- | By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality. | USB |
| IO20 | USB_D+ | By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality. | USB |
| IO26 | SPICS1 | Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO. | Flash |
| IO27 | SPIHD | Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO. | Flash |
| IO28 | SPIWP | Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO. | Flash |
| IO29 | SPICS0 | Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO. | Flash |
| IO30 | SPICLK | Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO. | Flash |
| IO31 | SPIQ | Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO. | Flash |
| IO32 | SPID | Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO. | Flash |
| IO33 | SPIIO4 (GPIO33) | The datasheet keeps GPIO33-37 for "the higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode", so octal-PSRAM modules (N16R8 and friends) consume it and do not break it out. On quad-PSRAM or PSRAM-less parts it is an ordinary GPIO - check which variant your module carries. | Flash |
| IO34 | SPIIO5 (GPIO34) | The datasheet keeps GPIO33-37 for "the higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode", so octal-PSRAM modules (N16R8 and friends) consume it and do not break it out. On quad-PSRAM or PSRAM-less parts it is an ordinary GPIO - check which variant your module carries. | Flash |
| IO35 | SPIIO6 (GPIO35) | The datasheet keeps GPIO33-37 for "the higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode", so octal-PSRAM modules (N16R8 and friends) consume it and do not break it out. On quad-PSRAM or PSRAM-less parts it is an ordinary GPIO - check which variant your module carries. | Flash |
| IO36 | SPIIO7 (GPIO36) | The datasheet keeps GPIO33-37 for "the higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode", so octal-PSRAM modules (N16R8 and friends) consume it and do not break it out. On quad-PSRAM or PSRAM-less parts it is an ordinary GPIO - check which variant your module carries. | Flash |
| IO37 | SPIDQS (GPIO37) | The datasheet keeps GPIO33-37 for "the higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode", so octal-PSRAM modules (N16R8 and friends) consume it and do not break it out. On quad-PSRAM or PSRAM-less parts it is an ordinary GPIO - check which variant your module carries. | Flash |
| IO39 | MTCK (GPIO39) | Default JTAG TCK - keep it free if you debug over JTAG. It is not a flash or PSRAM line on standard modules: those sit on GPIO26-37. | JTAG |
| IO40 | MTDO (GPIO40) | Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality. | JTAG |
| IO41 | MTDI (GPIO41) | Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available. | JTAG |
| IO42 | MTMS (GPIO42) | Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB). | JTAG |
| IO43 | U0TXD (GPIO43) | Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0). | UART |
| IO44 | U0RXD (GPIO44) | Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip. | UART |
| IO45 | GPIO45 | Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting. | Strapping |
| IO46 | GPIO46 | Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function. | Strapping |
| IO47 | SPICLK_P | Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48. | Other |
| IO48 | SPICLK_N | Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48. | Other |
ESP32-S3 modules & revisions
5 variants
ESP32-S3 boards
84 boards
