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CYD ESP32-1732S019
An ESP32-S3-based development board by CYD, designed for display and user interface applications.
65 × 32 mm
ESP32-S3
MCU
240MHz
clock
16MB
flash
512KB
SRAM
20· 11 ADC
GPIO
BLE 5.0+ WiFi
radio
Pinout
24 pins
| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | 20 | IO20GPIO20 | uart | adc | P1 header pin 1; ESP32-S3 native USB D+ (USB-PWR-DP) |
| 2 | 19 | IO19GPIO19 | uart | adc | P1 header pin 2; ESP32-S3 native USB D- (USB-PWR-DM) |
| 3 | 18 | IO18GPIO18 | safe | adc | P1 header pin 3 |
| 4 | 17 | IO17GPIO17 | safe | adc | P1 header pin 4 |
| 5 | 16 | IO16GPIO16 | safe | adc | P1 header pin 5 |
| 6 | 15 | IO15GPIO15 | safe | adc | P1 header pin 6 |
| 7 | 7 | IO7GPIO7 | safe | adc · touch | P1 header pin 7 |
| 8 | 6 | IO6GPIO6 | safe | adc · touch | P1 header pin 8 |
| 9 | 5 | IO5GPIO5 | safe | adc · touch | P1 header pin 9 |
| 10 | 4 | IO4GPIO4 | safe | adc · touch | P1 header pin 10 |
| 11 | - | 3V33.3V | power | - | P1 header pin 11; 3.3V output |
| 12 | - | GND | ground | - | P1 header pin 12 |
| 13 | - | 5V | power | - | P2 header pin 1; 5V rail (USB VBUS) |
| 14 | - | GND | ground | - | P2 header pin 2 |
| 15 | 21 | IO21GPIO21 | safe | - | P2 header pin 3 |
| 16 | 47 | IO47GPIO47 | strapping | - | P2 header pin 4 |
| 17 | 48 | IO48GPIO48 | strapping | - | P2 header pin 5 |
| 18 | 45 | IO45GPIO45 | strapping | - | P2 header pin 6; strapping pin (VDD_SPI voltage select) |
| 19 | 38 | IO38GPIO38 | strapping | - | P2 header pin 7 |
| 20 | 39 | IO39GPIO39 | strapping | - | P2 header pin 8; JTAG MTCK |
| 21 | 40 | IO40GPIO40 | strapping | - | P2 header pin 9; JTAG MTDO |
| 22 | 41 | IO41GPIO41 | strapping | - | P2 header pin 10; JTAG MTDI |
| 23 | 42 | IO42GPIO42 | strapping | - | P2 header pin 11; JTAG MTMS |
| 24 | 2 | IO2GPIO2 | safe | adc · touch | P2 header pin 12 |
Start with these
10 pins with no boot or system involvementIO18GPIO18IO17GPIO17IO16GPIO16IO15GPIO15IO7GPIO7IO6GPIO6IO5GPIO5IO4GPIO4IO21GPIO21IO2GPIO2
Freely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
sampled at boot or shared with debug/serial| Pin | Label | What to know | Role |
|---|---|---|---|
| IO45 | GPIO45 | Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting. | Strapping |
| IO39 | MTCK (GPIO39) | Default JTAG debugging TCK pin. If JTAG is needed, this pin must be free; it may also be used internally for PSRAM chip select on certain modules, so avoid repurposing it. | Other |
| IO40 | MTDO (GPIO40) | Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality. | Other |
| IO41 | MTDI (GPIO41) | Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available. | Other |
| IO42 | MTMS (GPIO42) | Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB). | Other |
Only if you know the tricks
wired to flash or USB - expect a fight| Pin | Label | What to know | Role |
|---|---|---|---|
| IO20 | USB_D+ | By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality. | USB |
| IO19 | USB_D- | By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality. | USB |
| IO47 | SPICLK_P | Used only on variants with Octal SPI interface (e.g. ESP32-S3R16V) as part of the differential clock pair. On such chips it operates at 1.8 V and is reserved for the high-speed octal SPI clock, not for general GPIO use. | Flash |
| IO48 | SPICLK_N | Used only on variants with Octal SPI interface, as the negative leg of the differential clock&. On such chips it operates at 1.8 V; it should be avoided for GPIO to prevent conflicts with the octal flash/PSRAM clock. | Flash |
| IO38 | FSPIWP | On flash-equipped chips, this pin is tied to the flash’s WP# (or D3) line. It should be avoided for other use, as it’s needed for flash operations. | Flash |
These are recommendations, not hard rules - with the right pull-ups, timing and boot-state awareness most pins can be made to work. When in doubt, start green.
Pinout notes Across 24 pins, the CYD ESP32-1732S019 exposes 20 GPIO plus 3V3 , GND and 5V for power. Beyond plain digital I/O you get 11 ADC-capable pins for sensors and…
Across 24 pins, the CYD ESP32-1732S019 exposes 20 GPIO plus 3V3, GND and 5V for power.
Beyond plain digital I/O you get 11 ADC-capable pins for sensors and battery monitoring and 5 capacitive-touch inputs.
5 of the exposed pins carry boot-time or system duties on the ESP32-S3 (IO45, IO39, IO40 and 2 more) - check the guidance above before wiring anything to them. IO18, IO17, IO16, IO15 and 6 more are free of any such role - the safest first picks.
Getting started
flash your first firmware in ~2 minutes1
Connect over USB
Serial chip: onboard. Not detected? Hold BOOT while plugging in.
2
Flash with your tool
Arduino IDE, PlatformIO, ESPHome or esptool - copy the settings on the right.
3
Verify it runs
The blink example uses GPIO18 - swap for your board's LED pin if different.
Board: Cyd Esp32 1732s019
Flash Size: 16MB · DIO
Upload Speed: 921600
// blink
pinMode(18, OUTPUT);
digitalWrite(18, LOW); // on (often inverted)[env:cyd-esp32-1732s019]
platform = espressif32
board = esp32-s3-devkitc-1
framework = arduino
monitor_speed = 115200
upload_speed = 921600esp32:
board: esp32-s3-devkitc-1
variant: cyd_esp32_1732s019
framework:
type: esp-idf
# blink - GPIO18
output:
- platform: gpio
pin: 18
id: led_out
light:
- platform: binary
name: "LED"
output: led_outesptool.py --chip esp32s3 --port /dev/ttyACM0 \
write_flash 0x0 firmware.binBuild details: sketch space 3145728 B · data 327680 B · DIO
Specifications
ESP32-S3 · 65 × 32 mmCompute
MCU
ESP32-S3
Clock
240 MHz
SRAM · Flash
512 KB · 16MB · 8MB (OPI) PSRAM
Radio
Wi-Fi
802.11 b/g/n
Bluetooth
5.0 LE
Antenna
PCB
I/O
GPIO · ADC
20 · 11
UART · I²C · SPI
3 · 2 · 4
PWM
8 channels
Power
USB
USB-C
Serial
-
Boot address
0x0
Display
Screen
IPS LCD · 1.9" · 170x320
Driver
ST7789
Touch
No
Flashing
Upload · OTA
esptool_py · esp_ota
Flash · Boot mode
DIO · QIO
Sketch · Data
3 MB · 320 KB
65 × 32 mm
The CYD ESP32-1732S019 uses esptool_py for firmware uploads, esp_ota for over-the-air (OTA) updates. Flash mode is DIO with QIO boot mode. The maximum sketch size is 3 MB with 320 KB available for data.
About this board
Inside sits the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads. Sibling CYD boards cover the ESP32-C3 and ESP32, so you can change radios or horsepower without changing the footprint.
At $10.49 it's cheaper than most CYD boards, which usually run around $22.
Around the module: 8MB (OPI) PSRAM, an IPS LCD 1.9" 170x320 display, a microSD slot and Reset/Boot buttons.
- A capacitive touch variant (ESP32-1732S019C, GT911) is also available
Where to buy
prices are typical street pricesCYD ESP32-1732S019
$10.49per unit, typical
Resources
Board datasheet surenoo.com↗ ESP32-S3 datasheet espressif.com↗ Surenoo ESP32-1732S019 product page (ESP32-S3 N16R8) surenoo.com↗PlatformIO Sunton board definitions (esp32-1732S019) github.com↗Sunton ESP32-1732S019N board definition (display/touch pin map) raw.githubusercontent.com↗Sunton ESP32-1732S019 schematic V1.0 (P1/P2 header pinout) github.com↗openHASP Sunton ESP32-1732S019 openhasp.com↗
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