LilyGo T3S3 V1.0
An ESP32-S3-based board designed for general-purpose applications, offering a balance of features and connectivity.
LilyGo T3S3 V1.0 Pinout
24 pins · 2.54 mm pitch
| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | 16 | IO16GPIO16U0CTSADC2_CH5 | uart | adc · uart · pwm | Left header; ADC2_CH5, UART0 CTS |
| 2 | 15 | IO15GPIO15U0RTSADC2_CH4 | uart | adc · uart · pwm | Left header; ADC2_CH4, UART0 RTS |
| 3 | - | RST | control | - | Left header; chip reset (EN) |
| 4 | 18 | IO18GPIO18SDAU1RXDADC2_CH7 | uart | adc · i2c · uart · pwm | Left header; I2C SDA shared with the SSD1306 OLED and QWIIC bus, ADC2_CH7 |
| 5 | 12 | IO12GPIO12FSPI_CLKTOUCH12ADC2_CH1 | strapping | adc · touch · spi · pwm | Left header; ADC2_CH1, capacitive touch, FSPI CLK |
| 6 | 48 | IO48GPIO48 | strapping | pwm | Left header; general-purpose IO |
| 7 | 47 | IO47GPIO47 | strapping | pwm | Left header; general-purpose IO |
| 8 | 35 | IO35GPIO35FSPI_D | safe | spi · pwm | Left header; FSPI D |
| 9 | 0 | IO0GPIO0 | strapping | pwm | Left header; BOOT button, strapping pin |
| 10 | 36 | IO36GPIO36FSPI_CLK | safe | spi · pwm | Left header; FSPI CLK |
| 11 | 37 | IO37GPIO37FSPI_Q | safe | spi · pwm | Left header; also drives the on-board LED, FSPI Q |
| 12 | 38 | IO38GPIO38 | safe | pwm | Right header; general-purpose IO |
| 13 | 43 | TXDGPIO43U0TXDCLK_OUT1 | uart | uart · pwm | Right header; default UART0 TX, also on the QWIIC socket |
| 14 | 44 | RXDGPIO44U0RXDCLK_OUT2 | uart | uart · pwm | Right header; default UART0 RX, also on the QWIIC socket |
| 15 | 39 | IO39GPIO39CLK_OUT2 | strapping | pwm | Right header; general-purpose IO |
| 16 | 40 | IO40GPIO40CLK_OUT3 | strapping | pwm | Right header; general-purpose IO |
| 17 | 41 | IO41GPIO41 | strapping | pwm | Right header; general-purpose IO |
| 18 | 45 | IO45GPIO45 | strapping | pwm | Right header; strapping pin |
| 19 | 46 | IO46GPIO46 | strapping | pwm | Right header; strapping pin |
| 20 | 42 | IO42GPIO42 | strapping | pwm | Right header; general-purpose IO |
| 21 | - | GND | ground | - | Right header |
| 22 | - | 3.3V | power | - | Right header; 3.3V output |
| 23 | - | GND | ground | - | Right header |
| 24 | - | 5V | power | - | Right header; 5V (VBUS) input/output |
Start with these
7 pins with no boot or system involvementFreely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
12 pins · 11 things to knowIO12 General-purpose SPI2 (FSPI) IO MUX pin - clock (FSPICLK) Other
IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI.
IO48IO47 Octal SPI differential clock legs (SPICLK_P/N_DIFF), used only by the 1.8 V octal flash/PSRAM variants Other
Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48.
- IO48Octal SPI differential clock negative leg (SPICLK_N_DIFF), used only by the 1.8 V octal flash/PSRAM variants
- IO47Octal SPI differential clock positive leg (SPICLK_P_DIFF), used only by the 1.8 V octal flash/PSRAM variants
IO0 Bootstrapping pin (Chip boot mode selection) Strapping
Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration.
TXDGPIO43 UART0 transmit pin (U0TXD), default serial console TX UART
Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0).
RXDGPIO44 UART0 receive pin (U0RXD), default serial console RX UART
Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip.
IO39 JTAG test clock (MTCK); IO MUX alternates CLK_OUT3 and SUBSPICS1 (chip select on the alternative SUBSPI memory bus, unused on standard modules) JTAG
Default JTAG TCK - keep it free if you debug over JTAG. It is not a flash or PSRAM line on standard modules: those sit on GPIO26-37.
IO40 JTAG test data out pin (MTDO) JTAG
Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality.
IO41 JTAG test data in pin (MTDI) JTAG
Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available.
IO45 Bootstrapping pin (selects VDD_SPI flash voltage) Strapping
Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting.
IO46 Bootstrapping pin (used with GPIO0 for boot mode; controls ROM log output) Strapping
Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function.
IO42 JTAG test mode select pin (MTMS) JTAG
Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB).
The LilyGo T3S3 V1.0 pinout brings out 24 pins at a 2.54 mm pitch - 19 usable GPIO alongside the GND, 3.3V and 5V power rails.
Beyond plain digital I/O you get 4 ADC-capable pins for sensors and battery monitoring, PWM on every GPIO and 1 capacitive-touch inputs.
12 of the exposed pins carry boot-time or system duties on the ESP32-S3 (IO12, IO48, IO47 and 9 more) - check the guidance above before wiring anything to them. IO16, IO15, IO18, IO35 and 3 more are free of any such role - the safest first picks.
Getting started
flash your first firmware in ~2 minutesBoard: ESP32S3 Dev Module USB CDC On Boot: Enabled Flash Size: 4MB (32Mb) Flash Mode: DIO PSRAM: QSPI PSRAM Partition Scheme: Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) Upload Speed: 921600
// toggle GPIO35 - wire an LED and resistor to it
void setup() {
pinMode(35, OUTPUT);
}
void loop() {
digitalWrite(35, HIGH); delay(500);
digitalWrite(35, LOW); delay(500);
}[env:lilygo_t3s3_v1_0]
platform = espressif32
board = esp32-s3-devkitc-1
framework = arduino
monitor_speed = 115200
upload_speed = 921600
board_build.arduino.memory_type = qio_qspi
build_flags = -DBOARD_HAS_PSRAMesp32-s3-devkitc-1 - or type it after board =.esp32:
board: esp32-s3-devkitc-1
variant: esp32s3
framework:
type: esp-idf
psram:
mode: quad
speed: 80MHz
# blink - GPIO35
output:
- platform: gpio
pin: 35
id: led_out
light:
- platform: binary
name: "LED"
output: led_outesp32-s3-devkitc-1 (same ids as PlatformIO).esptool.py --chip esp32s3 --port /dev/ttyACM0 \
--baud 921600 write_flash 0x0 firmware.bin--port = your /dev/tty* (macOS/Linux) or COMx (Windows).Specifications
ESP32-S3 · 66 × 36 mm · vs other ESP32 chips →Dimensions
About this board
Inside sits the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads.
The $29.99 price tag is typical for an ESP32-S3 board.
Around the module: 2MB (QSPI) PSRAM, an OLED 0.96" 128x64 display, a microSD slot, a Qwiic connector, LoRa (SX1262), battery charging via JST 1.25 and Reset/Boot buttons.
It flashes over native USB - no serial-converter driver needed, which isn't a given among ESP32-S3 boards.
- Ships in swappable Semtech RF variants: SX1262, SX1276, SX1278, SX1280 (2.4 GHz) and LR1121
- Sub-GHz (433 / 868 / 915 MHz) and 2.4 GHz LoRa options depending on RF module
- External LoRa antenna connector (RF module is socketed)
- 2x QWIIC (I2C) connectors plus a 2x13 2.54mm GPIO expansion header
- ESP32-S3FH4R2 with 4MB flash and 2MB PSRAM (both Quad-SPI)
Where to buy
prices are typical street pricesResources
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