LilyGo T3S3 V1.0
by LilyGo
An ESP32-S3-based board designed for general-purpose applications, offering a balance of features and connectivity.

On this page
Pinout
24 pins · 2.54 mm pitch| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | 16 | IO16GPIO16U0CTSADC2_CH5 | uart | adc · uart · pwm | Left header; ADC2_CH5, UART0 CTS |
| 2 | 15 | IO15GPIO15U0RTSADC2_CH4 | uart | adc · uart · pwm | Left header; ADC2_CH4, UART0 RTS |
| 3 | - | RST | control | - | Left header; chip reset (EN) |
| 4 | 18 | IO18GPIO18SDAU1RXDADC2_CH7 | uart | adc · i2c · uart · pwm | Left header; I2C SDA shared with the SSD1306 OLED and QWIIC bus, ADC2_CH7 |
| 5 | 12 | IO12GPIO12FSPI_CLKTOUCH12ADC2_CH1 | strapping | adc · touch · spi · pwm | Left header; ADC2_CH1, capacitive touch, FSPI CLK |
| 6 | 48 | IO48GPIO48 | strapping | pwm | Left header; general-purpose IO |
| 7 | 47 | IO47GPIO47 | strapping | pwm | Left header; general-purpose IO |
| 8 | 35 | IO35GPIO35FSPI_D | strapping | spi · pwm | Left header; FSPI D |
| 9 | 0 | IO0GPIO0 | strapping | pwm | Left header; BOOT button, strapping pin |
| 10 | 36 | IO36GPIO36FSPI_CLK | strapping | spi · pwm | Left header; FSPI CLK |
| 11 | 37 | IO37GPIO37FSPI_Q | strapping | spi · pwm | Left header; also drives the on-board LED, FSPI Q |
| 12 | 38 | IO38GPIO38 | strapping | pwm | Right header; general-purpose IO |
| 13 | 43 | TXDGPIO43U0TXDCLK_OUT1 | strapping | uart · pwm | Right header; default UART0 TX, also on the QWIIC socket |
| 14 | 44 | RXDGPIO44U0RXDCLK_OUT2 | strapping | uart · pwm | Right header; default UART0 RX, also on the QWIIC socket |
| 15 | 39 | IO39GPIO39CLK_OUT2 | strapping | pwm | Right header; general-purpose IO |
| 16 | 40 | IO40GPIO40CLK_OUT3 | strapping | pwm | Right header; general-purpose IO |
| 17 | 41 | IO41GPIO41 | strapping | pwm | Right header; general-purpose IO |
| 18 | 45 | IO45GPIO45 | strapping | pwm | Right header; strapping pin |
| 19 | 46 | IO46GPIO46 | strapping | pwm | Right header; strapping pin |
| 20 | 42 | IO42GPIO42 | strapping | pwm | Right header; general-purpose IO |
| 21 | - | GND | ground | - | Right header |
| 22 | - | 3.3V | power | - | Right header; 3.3V output |
| 23 | - | GND | ground | - | Right header |
| 24 | - | 5V | power | - | Right header; 5V (VBUS) input/output |
Start with these
3 pins with no boot or system involvementFreely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
sampled at boot or shared with debug/serial| Pin | Label | What to know | Role |
|---|---|---|---|
| IO0 | GPIO0 | Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration. | Strapping |
| TXD | U0TXD (GPIO43) | Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0). | Other |
| RXD | U0RXD (GPIO44) | Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip. | Other |
| IO39 | MTCK (GPIO39) | Default JTAG debugging TCK pin. If JTAG is needed, this pin must be free; it may also be used internally for PSRAM chip select on certain modules, so avoid repurposing it. | Other |
| IO40 | MTDO (GPIO40) | Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality. | Other |
| IO41 | MTDI (GPIO41) | Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available. | Other |
| IO45 | GPIO45 | Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting. | Strapping |
| IO46 | GPIO46 | Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function. | Strapping |
| IO42 | MTMS (GPIO42) | Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB). | Other |
Only if you know the tricks
wired to flash or USB - expect a fight| Pin | Label | What to know | Role |
|---|---|---|---|
| IO12 | FSPICLK | Drives the flash (and PSRAM) clock. This critical signal must be reserved for memory and not used as general GPIO. | Flash |
| IO48 | SPICLK_N | Used only on variants with Octal SPI interface, as the negative leg of the differential clock&. On such chips it operates at 1.8 V; it should be avoided for GPIO to prevent conflicts with the octal flash/PSRAM clock. | Flash |
| IO47 | SPICLK_P | Used only on variants with Octal SPI interface (e.g. ESP32-S3R16V) as part of the differential clock pair. On such chips it operates at 1.8 V and is reserved for the high-speed octal SPI clock, not for general GPIO use. | Flash |
| IO35 | FSPID / PSRAM_D0 | In modules with octal PSRAM, this pin is connected to the PSRAM data line. It is reserved for memory interface and not free for general GPIO when flash/PSRAM is present. | Flash |
| IO36 | FSPICLK / PSRAM_CLK | In modules with octal PSRAM, this pin drives the PSRAM clock. It must be dedicated to the memory interface, not used as a regular GPIO when that interface is in use. | Flash |
| IO37 | FSPIQ / PSRAM_DQS | In modules with octal PSRAM, this pin is connected to the PSRAM’s DQS signal. It cannot be repurposed without disrupting the PSRAM/flash communication. | Flash |
| IO38 | FSPIWP | On flash-equipped chips, this pin is tied to the flash’s WP# (or D3) line. It should be avoided for other use, as it’s needed for flash operations. | Flash |
Pinout notes The LilyGo T3S3 V1.0 pinout brings out 24 pins at a 2.54 mm pitch - 19 usable GPIO alongside the GND , 3.3V and 5V power rails. Beyond plain digital I/O you…
The LilyGo T3S3 V1.0 pinout brings out 24 pins at a 2.54 mm pitch - 19 usable GPIO alongside the GND, 3.3V and 5V power rails.
Beyond plain digital I/O you get 4 ADC-capable pins for sensors and battery monitoring, PWM on every GPIO and 1 capacitive-touch inputs.
9 of the exposed pins carry boot-time or system duties on the ESP32-S3 (IO0, TXD, RXD and 6 more) - check the guidance above before wiring anything to them. IO16, IO15 and IO18 are free of any such role - the safest first picks.
Getting started
flash your first firmware in ~2 minutesBoard: ESP32S3 Dev Module USB CDC On Boot: Enabled Flash Size: 4MB (32Mb) Flash Mode: DIO PSRAM: QSPI PSRAM Partition Scheme: Default 4MB with spiffs (1.2MB APP / 1.5MB SPIFFS) Upload Speed: 921600
// blink the onboard LED
void setup() {
pinMode(8, OUTPUT);
}
void loop() {
digitalWrite(8, HIGH); delay(500);
digitalWrite(8, LOW); delay(500);
}[env:lilygo_t3s3_v1_0]
platform = espressif32
board = esp32-s3-devkitc-1
framework = arduino
monitor_speed = 115200
upload_speed = 921600
board_build.arduino.memory_type = qio_qspi
build_flags = -DBOARD_HAS_PSRAMesp32-s3-devkitc-1 — or type it after board =.esp32:
board: esp32-s3-devkitc-1
variant: lilygo_t3s3_v1_0
framework:
type: esp-idf
psram:
mode: quad
speed: 80MHz
# blink - GPIO8
output:
- platform: gpio
pin: 8
id: led_out
light:
- platform: binary
name: "LED"
output: led_outesp32-s3-devkitc-1 (same ids as PlatformIO).esptool.py --chip esp32s3 --port /dev/ttyACM0 \
--baud 921600 write_flash 0x0 firmware.bin--port = your /dev/tty* (macOS/Linux) or COMx (Windows).Specifications
ESP32-S3 · 66 × 36 mmAbout this board
Inside sits the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads.
The $29.99 price tag is typical for an ESP32-S3 board.
Around the module: 2MB (QSPI) PSRAM, an OLED 0.96" 128x64 display, a microSD slot, a Qwiic connector, LoRa (SX1262), battery charging via JST 1.25 and Reset/Boot buttons.
It flashes over native USB - no serial-converter driver needed, which isn't a given among ESP32-S3 boards.
- Ships in swappable Semtech RF variants: SX1262, SX1276, SX1278, SX1280 (2.4 GHz) and LR1121
- Sub-GHz (433 / 868 / 915 MHz) and 2.4 GHz LoRa options depending on RF module
- External LoRa antenna connector (RF module is socketed)
- 2x QWIIC (I2C) connectors plus a 2x13 2.54mm GPIO expansion header
- ESP32-S3FH4R2 with 4MB flash and 2MB PSRAM (both Quad-SPI)
Where to buy
prices are typical street prices
Resources
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