Edgebox-ESP-100
An industrial-grade ESP32-S3 development board designed for edge computing and IoT gateway applications.
Edgebox-ESP-100 Pinout
34 pins| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | 0 | RST | strapping | - | |
| 2 | 1 | CAN_TXDPWM | safe | - | |
| 3 | 2 | CAN_RXDPWM | safe | - | |
| 4 | 4 | DI0PWM | safe | - | |
| 5 | 5 | DI1PWM | safe | - | |
| 6 | 6 | DI2PWM | safe | - | |
| 7 | 7 | DI3PWM | safe | - | |
| 8 | 8 | RS485_RTSPWM | safe | - | |
| 9 | 9 | I2C_INTPWM | strapping | - | |
| 10 | 10 | SSPWM | strapping | spi | |
| 11 | 11 | MISOPWM | strapping | spi | |
| 12 | 12 | MOSIPWM | strapping | spi | |
| 13 | 13 | SCKPWM | strapping | spi | |
| 14 | 14 | ETH_INTPWM | strapping | - | |
| 15 | 15 | ETH_RSTPWM | safe | - | |
| 16 | 16 | LTE_PWR_ENPWM | safe | - | |
| 17 | 17 | RS485_TXDPWM | safe | - | |
| 18 | 18 | RS485_RXDPWM | safe | - | |
| 19 | 19 | SCLPWM | uart | i2c | |
| 20 | 20 | SDAPWM | uart | i2c | |
| 21 | 21 | LTE_PWR_KEYPWM | safe | - | |
| 22 | 35 | DO5 | safe | - | |
| 23 | 36 | DO4 | safe | - | |
| 24 | 37 | DO3 | safe | - | |
| 25 | 38 | DO2 | safe | - | |
| 26 | 39 | DO1 | strapping | - | |
| 27 | 40 | DO0 | strapping | - | |
| 28 | 41 | AO1 | strapping | - | |
| 29 | 42 | AO0 | strapping | - | |
| 30 | 43 | TXD | uart | - | |
| 31 | 44 | RXD | uart | - | |
| 32 | 45 | BUZZER | strapping | - | |
| 33 | 47 | LTE_RXD | strapping | - | |
| 34 | 48 | LTE_TXD | strapping | - |
Start with these
16 pins with no boot or system involvementFreely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
16 pins · 10 things to knowRSTGPIO0 Bootstrapping pin (Chip boot mode selection) Strapping
Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration.
I2C_INTGPIO9SSGPIO10MISOGPIO11MOSIGPIO12SCKGPIO13ETH_INTGPIO14 General-purpose SPI2 (FSPI) IO MUX pins Other
IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI.
- I2C_INTGeneral-purpose SPI2 (FSPI) IO MUX pin - hold/data line (FSPIHD)
- SSGeneral-purpose SPI2 (FSPI) IO MUX pin - chip select (FSPICS0)
- MISOGeneral-purpose SPI2 (FSPI) IO MUX pin - data in (FSPID)
- MOSIGeneral-purpose SPI2 (FSPI) IO MUX pin - clock (FSPICLK)
- SCKGeneral-purpose SPI2 (FSPI) IO MUX pin - data out (FSPIQ)
- ETH_INTGeneral-purpose SPI2 (FSPI) IO MUX pin - write-protect/data line (FSPIWP)
DO1GPIO39 JTAG test clock (MTCK); IO MUX alternates CLK_OUT3 and SUBSPICS1 (chip select on the alternative SUBSPI memory bus, unused on standard modules) JTAG
Default JTAG TCK - keep it free if you debug over JTAG. It is not a flash or PSRAM line on standard modules: those sit on GPIO26-37.
DO0GPIO40 JTAG test data out pin (MTDO) JTAG
Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality.
AO1GPIO41 JTAG test data in pin (MTDI) JTAG
Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available.
AO0GPIO42 JTAG test mode select pin (MTMS) JTAG
Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB).
TXDGPIO43 UART0 transmit pin (U0TXD), default serial console TX UART
Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0).
RXDGPIO44 UART0 receive pin (U0RXD), default serial console RX UART
Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip.
BUZZERGPIO45 Bootstrapping pin (selects VDD_SPI flash voltage) Strapping
Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting.
LTE_RXDGPIO47LTE_TXDGPIO48 Octal SPI differential clock legs (SPICLK_P/N_DIFF), used only by the 1.8 V octal flash/PSRAM variants Other
Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48.
- LTE_RXDOctal SPI differential clock positive leg (SPICLK_P_DIFF), used only by the 1.8 V octal flash/PSRAM variants
- LTE_TXDOctal SPI differential clock negative leg (SPICLK_N_DIFF), used only by the 1.8 V octal flash/PSRAM variants
Only if you know the tricks
2 pins · 1 thing to knowSCLGPIO19SDAGPIO20 USB OTG differential data pair (D- and D+) USB
By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality.
- SCLUSB OTG negative differential data line (USB_D-)
- SDAUSB OTG positive differential data line (USB_D+)
All 34 pins on the Edgebox-ESP-100 are usable GPIO.
Peripheral wiring is straightforward: I²C is mapped to SDA on GPIO20 and SCL on GPIO19, while the SPI bus (MOSI, MISO, SCK, SS) is broken out in full.
16 of the exposed pins carry boot-time or system duties on the ESP32-S3 (RST, I2C_INT, SS and 13 more) - check the guidance above before wiring anything to them. CAN_TXD, CAN_RXD, DI0, DI1 and 12 more are free of any such role - the safest first picks.
Getting started
flash your first firmware in ~2 minutesBoard: ESP32S3 Dev Module USB CDC On Boot: Enabled Flash Size: 16MB (128Mb) Flash Mode: DIO PSRAM: QSPI PSRAM Partition Scheme: 16M Flash (3MB APP/9.9MB FATFS) Upload Speed: 921600
// toggle GPIO1 - wire an LED and resistor to it
void setup() {
pinMode(1, OUTPUT);
}
void loop() {
digitalWrite(1, HIGH); delay(500);
digitalWrite(1, LOW); delay(500);
}[env:Edgebox-ESP-100]
platform = espressif32
board = esp32-s3-devkitc-1
framework = arduino
monitor_speed = 115200
upload_speed = 921600
board_build.arduino.memory_type = qio_qspi
build_flags = -DBOARD_HAS_PSRAMesp32-s3-devkitc-1 - or type it after board =.esp32:
board: esp32-s3-devkitc-1
variant: esp32s3
framework:
type: esp-idf
psram:
mode: quad
speed: 80MHz
# blink - GPIO1
output:
- platform: gpio
pin: 1
id: led_out
light:
- platform: binary
name: "LED"
output: led_outesp32-s3-devkitc-1 (same ids as PlatformIO).esptool.py --chip esp32s3 --port /dev/ttyACM0 \
--baud 921600 write_flash 0x0 firmware.bin--port = your /dev/tty* (macOS/Linux) or COMx (Windows).Specifications
ESP32-S3 · 124 × 92 mm · vs other ESP32 chips →Dimensions
About this board
Inside sits the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads.
At $153.00 it's on the expensive side for an ESP32-S3 board - most land around $29.
With 34 GPIO broken out, you get more pins to play with than most ESP32-S3 boards offer.
Around the module: 8MB (QSPI) PSRAM, a PCF8563 RTC, a buzzer, an RS485 interface, a CAN bus interface, cellular connectivity (SIMCom A7670G) and wired Ethernet (W5500).
It flashes over native USB - no serial-converter driver needed, which isn't a given among ESP32-S3 boards.
- 4 isolated digital inputs (24V) and 6 isolated digital outputs
- 4 isolated analog inputs (0-20mA / 0-10V) and 2 isolated analog outputs (0-5V)
- Isolated RS485 and CAN Bus with onboard 120Ω termination
- SIMCom A7670G 4G LTE Cat-1 cellular modem
- ATECC608A crypto element and FM24CL64B FRAM (non-volatile retain memory)
- SGM58031 16-bit ADC for the isolated analog inputs
- Industrial enclosure, operating temperature -20 to 60°C
Where to buy
prices are typical street pricesResources
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