Espressif ESP32-S3-DevKitC-1
Full-featured ESP32-S3 dev board with USB, PSRAM, and rich I/O - perfect for AIoT prototyping and embedded apps.
Espressif ESP32-S3-DevKitC-1 Pinout
44 pins · 2.54 mm pitch
| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | - | 3V33.3V | power | - | 3.3V regulated output |
| 2 | - | 3V33.3V | power | - | 3.3V regulated output |
| 3 | - | RSTEN | control | - | Chip reset (active low) |
| 4 | 4 | IO4A4T4 | safe | adc · touch · pwm | ADC1_CH3; TOUCH4; RTC |
| 5 | 5 | IO5A5T5 | safe | adc · touch · pwm | ADC1_CH4; TOUCH5; RTC |
| 6 | 6 | IO6A6T6 | safe | adc · touch · pwm | ADC1_CH5; TOUCH6; RTC |
| 7 | 7 | IO7A7T7 | safe | adc · touch · pwm | ADC1_CH6; TOUCH7; RTC |
| 8 | 15 | IO15A15 | uart | adc · uart · pwm | ADC2_CH4; UART0 RTS; XTAL_32K_P; RTC |
| 9 | 16 | IO16A16 | uart | adc · uart · pwm | ADC2_CH5; UART0 CTS; XTAL_32K_N; RTC |
| 10 | 17 | IO17A17 | uart | adc · uart · pwm | ADC2_CH6; UART1 TX; RTC |
| 11 | 18 | IO18A18 | uart | adc · uart · pwm | ADC2_CH7; UART1 RX; CLK_OUT3; RTC |
| 12 | 8 | IO8A8T8 | safe | adc · touch · pwm | ADC1_CH7; TOUCH8; RTC |
| 13 | 3 | IO3A3T3 | strapping | adc · touch · pwm | ADC1_CH2; TOUCH3; JTAG; RTC |
| 14 | 46 | IO46 | strapping | pwm | General-purpose GPIO; ROM log control |
| 15 | 9 | IO9A9T9 | strapping | adc · touch · spi · pwm | ADC1_CH8; TOUCH9; FSPIHD; RTC |
| 16 | 10 | IO10A10T10SS | strapping | adc · touch · spi · pwm | ADC1_CH9; TOUCH10; FSPICS0 (default SPI SS); RTC |
| 17 | 11 | IO11A11T11MOSI | strapping | adc · touch · spi · pwm | ADC2_CH0; TOUCH11; FSPID (default SPI MOSI); RTC |
| 18 | 12 | IO12A12T12SCK | strapping | adc · touch · spi · pwm | ADC2_CH1; TOUCH12; FSPICLK (default SPI SCK); RTC |
| 19 | 13 | IO13A13T13MISO | strapping | adc · touch · spi · pwm | ADC2_CH2; TOUCH13; FSPIQ (default SPI MISO); RTC |
| 20 | 14 | IO14A14T14 | strapping | adc · touch · spi · pwm | ADC2_CH3; TOUCH14; FSPIWP; RTC |
| 21 | - | 5V | power | - | 5V input (from USB) / output |
| 22 | - | GND | ground | - | Ground |
| 23 | - | GND | ground | - | Ground |
| 24 | 43 | IO43TX | uart | uart · pwm | UART0 TX; CLK_OUT1 |
| 25 | 44 | IO44RX | uart | uart · pwm | UART0 RX; CLK_OUT2 |
| 26 | 1 | IO1A1T1 | safe | adc · touch · pwm | ADC1_CH0; TOUCH1; RTC |
| 27 | 2 | IO2A2T2 | safe | adc · touch · pwm | ADC1_CH1; TOUCH2; RTC |
| 28 | 42 | IO42 | strapping | pwm | JTAG MTMS |
| 29 | 41 | IO41 | strapping | pwm | JTAG MTDI; CLK_OUT1 |
| 30 | 40 | IO40 | strapping | pwm | JTAG MTDO; CLK_OUT2 |
| 31 | 39 | IO39 | strapping | pwm | JTAG MTCK; CLK_OUT3 |
| 32 | 38 | IO38 | safe | spi · pwm | Onboard RGB LED (v1.1); FSPIWP |
| 33 | 37 | IO37 | strapping | spi · pwm | SPIDQS; FSPIQ; octal PSRAM on R8/R16 variants |
| 34 | 36 | IO36 | strapping | spi · pwm | SPIIO7; FSPICLK; octal PSRAM on R8/R16 variants |
| 35 | 35 | IO35 | strapping | spi · pwm | SPIIO6; FSPID; octal PSRAM on R8/R16 variants |
| 36 | 0 | IO0 | strapping | pwm | Onboard BOOT button |
| 37 | 45 | IO45 | strapping | pwm | General-purpose GPIO |
| 38 | 48 | IO48 | strapping | pwm | SPICLK_N; RGB LED on early v1.0 boards |
| 39 | 47 | IO47 | strapping | pwm | SPICLK_P |
| 40 | 21 | IO21 | safe | pwm | General-purpose GPIO; RTC |
| 41 | 20 | IO20A20 | uart | adc · uart · pwm | USB D+ (native USB); ADC2_CH9; UART1 CTS; RTC |
| 42 | 19 | IO19A19 | uart | adc · uart · pwm | USB D- (native USB); ADC2_CH8; UART1 RTS; RTC |
| 43 | - | GND | ground | - | Ground |
| 44 | - | GND | ground | - | Ground |
Start with these
13 pins with no boot or system involvementFreely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
18 pins · 12 things to knowIO3 Bootstrapping pin (controls JTAG signal source) Strapping
Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface.
IO46 Bootstrapping pin (used with GPIO0 for boot mode; controls ROM log output) Strapping
Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function.
IO9IO10IO11IO12IO13IO14 General-purpose SPI2 (FSPI) IO MUX pins Other
IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI.
- IO9General-purpose SPI2 (FSPI) IO MUX pin - hold/data line (FSPIHD)
- IO10General-purpose SPI2 (FSPI) IO MUX pin - chip select (FSPICS0)
- IO11General-purpose SPI2 (FSPI) IO MUX pin - data in (FSPID)
- IO12General-purpose SPI2 (FSPI) IO MUX pin - clock (FSPICLK)
- IO13General-purpose SPI2 (FSPI) IO MUX pin - data out (FSPIQ)
- IO14General-purpose SPI2 (FSPI) IO MUX pin - write-protect/data line (FSPIWP)
IO43 UART0 transmit pin (U0TXD), default serial console TX UART
Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0).
IO44 UART0 receive pin (U0RXD), default serial console RX UART
Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip.
IO42 JTAG test mode select pin (MTMS) JTAG
Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB).
IO41 JTAG test data in pin (MTDI) JTAG
Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available.
IO40 JTAG test data out pin (MTDO) JTAG
Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality.
IO39 JTAG test clock (MTCK); IO MUX alternates CLK_OUT3 and SUBSPICS1 (chip select on the alternative SUBSPI memory bus, unused on standard modules) JTAG
Default JTAG TCK - keep it free if you debug over JTAG. It is not a flash or PSRAM line on standard modules: those sit on GPIO26-37.
IO0 Bootstrapping pin (Chip boot mode selection) Strapping
Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration.
IO45 Bootstrapping pin (selects VDD_SPI flash voltage) Strapping
Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting.
IO48IO47 Octal SPI differential clock legs (SPICLK_P/N_DIFF), used only by the 1.8 V octal flash/PSRAM variants Other
Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48.
- IO48Octal SPI differential clock negative leg (SPICLK_N_DIFF), used only by the 1.8 V octal flash/PSRAM variants
- IO47Octal SPI differential clock positive leg (SPICLK_P_DIFF), used only by the 1.8 V octal flash/PSRAM variants
Only if you know the tricks
5 pins · 2 things to knowIO37IO36IO35 Octal (8-line) flash/PSRAM data and strobe lines on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts Flash
The datasheet keeps GPIO33-37 for "the higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode", so octal-PSRAM modules (N16R8 and friends) consume it and do not break it out. On quad-PSRAM or PSRAM-less parts it is an ordinary GPIO - check which variant your module carries.
- IO37Octal (8-line) flash/PSRAM data strobe DQS/DM on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts
- IO36Octal (8-line) flash/PSRAM data line DQ7 on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts
- IO35Octal (8-line) flash/PSRAM data line DQ6 on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts
IO20IO19 USB OTG differential data pair (D- and D+) USB
By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality.
- IO20USB OTG positive differential data line (USB_D+)
- IO19USB OTG negative differential data line (USB_D-)
The Espressif ESP32-S3-DevKitC-1 breaks out 44 pins in total: 36 GPIO for your project, with 3V3, 5V and GND handling power.
Peripheral wiring is straightforward: the SPI bus (MOSI, MISO, SCK, SS) is broken out in full, while TX/RX on GPIO43 and GPIO44 cover serial logging and flashing.
Beyond plain digital I/O you get 20 ADC-capable pins for sensors and battery monitoring, PWM on every GPIO and 14 capacitive-touch inputs.
18 of the exposed pins carry boot-time or system duties on the ESP32-S3 (IO3, IO46, IO9 and 15 more) - check the guidance above before wiring anything to them. IO4, IO5, IO6, IO7 and 9 more are free of any such role - the safest first picks.
Getting started
flash your first firmware in ~2 minutesBoard: ESP32S3 Dev Module USB CDC On Boot: Enabled Flash Size: 8MB (64Mb) Flash Mode: DIO PSRAM: OPI PSRAM Partition Scheme: 8M with spiffs (3MB APP/1.5MB SPIFFS) Upload Speed: 921600
// toggle GPIO4 - wire an LED and resistor to it
void setup() {
pinMode(4, OUTPUT);
}
void loop() {
digitalWrite(4, HIGH); delay(500);
digitalWrite(4, LOW); delay(500);
}[env:esp32-s3-devkitc-1]
platform = espressif32
board = esp32-s3-devkitc-1
framework = arduino
monitor_speed = 115200
upload_speed = 921600
board_build.arduino.memory_type = qio_opi
build_flags = -DBOARD_HAS_PSRAMesp32-s3-devkitc-1 - or type it after board =.esp32:
board: esp32-s3-devkitc-1
variant: esp32s3
framework:
type: esp-idf
psram:
mode: octal
speed: 80MHz
# blink - GPIO4
output:
- platform: gpio
pin: 4
id: led_out
light:
- platform: binary
name: "LED"
output: led_outesp32-s3-devkitc-1 (same ids as PlatformIO).esptool.py --chip esp32s3 --port /dev/ttyACM0 \
--baud 921600 write_flash 0x0 firmware.bin--port = your /dev/tty* (macOS/Linux) or COMx (Windows).Downloads
Free for non-commercial use, credit espboards.dev · License
Board illustration
The bare Espressif ESP32-S3-DevKitC-1 board drawn to scale at 70 × 28 mm, with no pin labels on it. Made for slide decks, wiring diagrams and project write-ups where a photo is too busy. Take the scalable SVG for print or editing, the high-resolution PNG to drop straight in, or the transparent PNG when you need it with no background behind it.
Pinout diagram
Every pin on both sides of the board with its functions, drawn by ESPboards from the ESP32-S3 Series Datasheet v2.2 - the same sheet shown at the top of this page. The PNG is a high-resolution image for screens, the SVG is vector so it stays sharp at any size, and the PDF is laid out to print on A4 or Letter.
Yours to use, share and adapt for non-commercial work, as long as you credit espboards.dev - the full terms and ready-made credit lines are here.
Specifications
ESP32-S3 · 70 × 28 mm · vs other ESP32 chips →Dimensions
About this board
Inside sits the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads.
At $15.00 it's cheaper than most ESP32-S3 boards, which usually run around $29.
With 36 GPIO broken out, you get more pins to play with than most ESP32-S3 boards offer.
Around the module: 8MB (OPI) PSRAM, an addressable RGB LED (GPIO38) and Boot/Reset buttons.
- Sold in memory variants: N8 (8MB flash, no PSRAM), N8R2 (8MB flash + 2MB quad PSRAM), N8R8 (8MB flash + 8MB octal PSRAM), N16R8 (16MB flash + 8MB octal PSRAM)
- Addressable RGB LED on GPIO38 on board revision v1.1; early v1.0 boards and many clones drive it on GPIO48
- ESP32-S3-WROOM-1U variant swaps the PCB antenna for a u.FL external antenna connector
Where to buy
prices are typical street pricesResources
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