YD-ESP32-S3
Dual USB-C ESP32-S3-WROOM-1 dev board (DevKitC-1 clone) by VCC-GND Studio with 16MB flash, 8MB PSRAM, CH343P USB-serial and an addressable RGB LED.
YD-ESP32-S3 Pinout
44 pins · 2.54 mm pitch
| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | - | GND | ground | - | Ground |
| 2 | - | GND | ground | - | Ground |
| 3 | 19 | IO19 | uart | adc · pwm | Native USB D- |
| 4 | 20 | IO20 | uart | adc · pwm | Native USB D+ |
| 5 | 21 | IO21 | safe | pwm | |
| 6 | 47 | IO47 | strapping | pwm | |
| 7 | 48 | IO48 | strapping | pwm | Onboard WS2812 addressable RGB LED |
| 8 | 45 | IO45 | strapping | pwm | |
| 9 | 0 | IO0 | strapping | pwm | BOOT button |
| 10 | 35 | IO35 | strapping | pwm | Used by octal PSRAM on R8 variants |
| 11 | 36 | IO36 | strapping | pwm | Used by octal PSRAM on R8 variants |
| 12 | 37 | IO37 | strapping | pwm | Used by octal PSRAM on R8 variants |
| 13 | 38 | IO38 | safe | pwm | |
| 14 | 39 | IO39 | strapping | pwm | |
| 15 | 40 | IO40 | strapping | pwm | |
| 16 | 41 | IO41 | strapping | pwm | |
| 17 | 42 | IO42 | strapping | pwm | |
| 18 | 2 | IO2 | safe | adc · touch · pwm | |
| 19 | 1 | IO1 | safe | adc · touch · pwm | |
| 20 | 44 | RXIO44U0RXD | uart | uart · pwm | UART0 RX |
| 21 | 43 | TXIO43U0TXD | uart | uart · pwm | UART0 TX |
| 22 | - | GND | ground | - | Ground |
| 23 | - | GND | ground | - | Ground |
| 24 | - | 5V | power | - | 5V USB power in/out |
| 25 | 14 | IO14 | strapping | adc · touch · pwm | |
| 26 | 13 | IO13 | strapping | adc · touch · pwm | |
| 27 | 12 | IO12 | strapping | adc · touch · pwm | |
| 28 | 11 | IO11 | strapping | adc · touch · pwm | |
| 29 | 10 | IO10 | strapping | adc · touch · pwm | |
| 30 | 9 | IO9 | strapping | adc · touch · pwm | |
| 31 | 46 | IO46 | strapping | pwm | |
| 32 | 3 | IO3 | strapping | adc · touch · pwm | |
| 33 | 8 | IO8 | safe | adc · touch · pwm | |
| 34 | 18 | IO18 | safe | adc · pwm | |
| 35 | 17 | IO17 | safe | adc · pwm | |
| 36 | 16 | IO16 | safe | adc · pwm | |
| 37 | 15 | IO15 | safe | adc · pwm | |
| 38 | 7 | IO7 | safe | adc · touch · pwm | |
| 39 | 6 | IO6 | safe | adc · touch · pwm | |
| 40 | 5 | IO5 | safe | adc · touch · pwm | |
| 41 | 4 | IO4 | safe | adc · touch · pwm | |
| 42 | - | RSTEN | control | - | Reset (chip enable) |
| 43 | - | 3V3 | power | - | 3.3V output |
| 44 | - | 3V3 | power | - | 3.3V output |
Start with these
13 pins with no boot or system involvementFreely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
18 pins · 12 things to knowIO47IO48 Octal SPI differential clock legs (SPICLK_P/N_DIFF), used only by the 1.8 V octal flash/PSRAM variants Other
Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48.
- IO47Octal SPI differential clock positive leg (SPICLK_P_DIFF), used only by the 1.8 V octal flash/PSRAM variants
- IO48Octal SPI differential clock negative leg (SPICLK_N_DIFF), used only by the 1.8 V octal flash/PSRAM variants
IO45 Bootstrapping pin (selects VDD_SPI flash voltage) Strapping
Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting.
IO0 Bootstrapping pin (Chip boot mode selection) Strapping
Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration.
IO39 JTAG test clock (MTCK); IO MUX alternates CLK_OUT3 and SUBSPICS1 (chip select on the alternative SUBSPI memory bus, unused on standard modules) JTAG
Default JTAG TCK - keep it free if you debug over JTAG. It is not a flash or PSRAM line on standard modules: those sit on GPIO26-37.
IO40 JTAG test data out pin (MTDO) JTAG
Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality.
IO41 JTAG test data in pin (MTDI) JTAG
Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available.
IO42 JTAG test mode select pin (MTMS) JTAG
Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB).
RXGPIO44 UART0 receive pin (U0RXD), default serial console RX UART
Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip.
TXGPIO43 UART0 transmit pin (U0TXD), default serial console TX UART
Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0).
IO14IO13IO12IO11IO10IO9 General-purpose SPI2 (FSPI) IO MUX pins Other
IO MUX pin of the general-purpose SPI2 (FSPI) bus, not of the in-package flash - that sits on GPIO26-32. The datasheet lists it as a priority-2 pin ("can be freely used without restrictions"), so it is only taken if your board wires flash, an SD card or a display to FSPI.
- IO14General-purpose SPI2 (FSPI) IO MUX pin - write-protect/data line (FSPIWP)
- IO13General-purpose SPI2 (FSPI) IO MUX pin - data out (FSPIQ)
- IO12General-purpose SPI2 (FSPI) IO MUX pin - clock (FSPICLK)
- IO11General-purpose SPI2 (FSPI) IO MUX pin - data in (FSPID)
- IO10General-purpose SPI2 (FSPI) IO MUX pin - chip select (FSPICS0)
- IO9General-purpose SPI2 (FSPI) IO MUX pin - hold/data line (FSPIHD)
IO46 Bootstrapping pin (used with GPIO0 for boot mode; controls ROM log output) Strapping
Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function.
IO3 Bootstrapping pin (controls JTAG signal source) Strapping
Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface.
Only if you know the tricks
5 pins · 2 things to knowIO19IO20 USB OTG differential data pair (D- and D+) USB
By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality.
- IO19USB OTG negative differential data line (USB_D-)
- IO20USB OTG positive differential data line (USB_D+)
IO35IO36IO37 Octal (8-line) flash/PSRAM data and strobe lines on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts Flash
The datasheet keeps GPIO33-37 for "the higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode", so octal-PSRAM modules (N16R8 and friends) consume it and do not break it out. On quad-PSRAM or PSRAM-less parts it is an ordinary GPIO - check which variant your module carries.
- IO35Octal (8-line) flash/PSRAM data line DQ6 on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts
- IO36Octal (8-line) flash/PSRAM data line DQ7 on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts
- IO37Octal (8-line) flash/PSRAM data strobe DQS/DM on R8/R16V modules; free on quad-PSRAM and PSRAM-less parts
Across 44 pins (2.54 mm pitch), the YD-ESP32-S3 exposes 36 GPIO plus GND, 5V and 3V3 for power.
For peripherals, TX/RX on GPIO43 and GPIO44 cover serial logging and flashing.
On the analog side there are 20 ADC-capable pins for sensors and battery monitoring, PWM on every GPIO and 14 capacitive-touch inputs.
If you want zero surprises, IO21, IO38, IO2, IO1 and 9 more are free of any such role - the safest first picks. 18 of the exposed pins carry boot-time or system duties on the ESP32-S3 (IO47, IO48, IO45 and 15 more).
Getting started
flash your first firmware in ~2 minutesBoard: ESP32S3 Dev Module USB CDC On Boot: Enabled Flash Size: 16MB (128Mb) PSRAM: OPI PSRAM Partition Scheme: 16M Flash (3MB APP/9.9MB FATFS) Upload Speed: 921600
// toggle GPIO21 - wire an LED and resistor to it
void setup() {
pinMode(21, OUTPUT);
}
void loop() {
digitalWrite(21, HIGH); delay(500);
digitalWrite(21, LOW); delay(500);
}[env:yd-esp32-s3]
platform = espressif32
board = esp32-s3-devkitc-1
framework = arduino
monitor_speed = 115200
upload_speed = 921600
board_build.arduino.memory_type = qio_opi
build_flags = -DBOARD_HAS_PSRAMesp32-s3-devkitc-1 - or type it after board =.esp32:
board: esp32-s3-devkitc-1
variant: esp32s3
framework:
type: esp-idf
psram:
mode: octal
speed: 80MHz
# blink - GPIO21
output:
- platform: gpio
pin: 21
id: led_out
light:
- platform: binary
name: "LED"
output: led_outesp32-s3-devkitc-1 (same ids as PlatformIO).esptool.py --chip esp32s3 --port /dev/ttyACM0 \
--baud 921600 write_flash 0x0 firmware.bin--port = your /dev/tty* (macOS/Linux) or COMx (Windows).Specifications
ESP32-S3 · 63.5 × 28 mm · vs other ESP32 chips →Dimensions
About this board
At its core is the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads.
Expect to pay about $9.50 - less than the ~$29 most ESP32-S3 boards go for.
36 GPIO are broken out - more than most ESP32-S3 boards, so the pin budget is rarely the constraint.
Onboard you'll find 8MB (OPI) PSRAM, an addressable RGB LED (GPIO48) and Reset/Boot buttons.
- Also sold in N8R2 (8MB flash, 2MB PSRAM) and N8R8 (8MB flash, 8MB PSRAM) memory variants
Where to buy
prices are typical street prices
Resources
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