Heltec WiFi LoRa 32 (V3)
ESP32-S3 LoRa board with an SX1262 radio, 0.96" OLED and LiPo charger - the classic Meshtastic and LoRaWAN node.
Heltec WiFi LoRa 32 (V3) Pinout
45 pins · 2.54 mm pitch
| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | - | GND | ground | - | J2 pin 1 |
| 2 | - | 5V | power | - | USB 5 V - after the fuse on V3 / V3.1, before it on V3.2 |
| 3 | - | VeVext | power | - | Vext: switched 3.3 V output (350 mA), on while GPIO36 is LOW; it also powers the OLED |
| 4 | - | VeVext | power | - | Vext, second pin |
| 5 | 44 | GPIO44RXU0RXD | uart | uart · pwm | UART0 RX, wired to the CP2102 TX |
| 6 | 43 | GPIO43TXU0TXD | uart | uart · pwm | UART0 TX, wired to the CP2102 RX |
| 7 | - | RSTEN | control | - | chip reset (CHIP_PU), shared with the RST button |
| 8 | 0 | GPIO0PRG | strapping | pwm | the PRG / USER button (10K pull-up); strapping pin |
| 9 | 36 | GPIO36Vext_Ctrl | safe | pwm | Vext switch: LOW turns the Vext rail (and the OLED) on |
| 10 | 35 | GPIO35LED | safe | pwm | the white user LED through 330R, lit HIGH |
| 11 | 34 | GPIO34 | safe | pwm | |
| 12 | 33 | GPIO33 | safe | pwm | |
| 13 | 47 | GPIO47 | strapping | pwm | |
| 14 | 48 | GPIO48 | strapping | pwm | |
| 15 | 26 | GPIO26 | safe | pwm | |
| 16 | 21 | GPIO21OLED_RST | safe | pwm | OLED reset |
| 17 | 20 | GPIO20USB_D+ | uart | adc · pwm | native USB D+ is not connected to the USB-C (R29 not fitted), so this is a free GPIO |
| 18 | 19 | GPIO19USB_D- | uart | adc · pwm | native USB D- is not connected to the USB-C (R3 not fitted), so this is a free GPIO |
| 19 | - | GND | ground | - | J3 pin 1 |
| 20 | - | 3V3 | power | - | |
| 21 | - | 3V3 | power | - | |
| 22 | 37 | GPIO37ADC_Ctrl | safe | pwm | switches the battery-voltage divider onto GPIO1: HIGH to read on V3.2, LOW to read on V3 / V3.1 |
| 23 | 46 | GPIO46 | strapping | pwm | |
| 24 | 45 | GPIO45 | strapping | pwm | |
| 25 | 42 | GPIO42 | strapping | pwm | |
| 26 | 41 | GPIO41 | strapping | pwm | |
| 27 | 40 | GPIO40 | strapping | pwm | |
| 28 | 39 | GPIO39 | strapping | pwm | |
| 29 | 38 | GPIO38 | safe | pwm | |
| 30 | 1 | GPIO1VBAT_Read | safe | adc · touch · pwm | battery voltage through a 390K / 100K divider (battery = reading x 4.9) while GPIO37 enables it |
| 31 | 2 | GPIO2 | safe | adc · touch · pwm | |
| 32 | 3 | GPIO3 | strapping | adc · touch · pwm | |
| 33 | 4 | GPIO4 | safe | adc · touch · pwm | |
| 34 | 5 | GPIO5 | safe | adc · touch · pwm | |
| 35 | 6 | GPIO6 | safe | adc · touch · pwm | |
| 36 | 7 | GPIO7 | safe | adc · touch · pwm | |
| 37 | 8 | GPIO8LoRa_NSS | safe | adc · touch · pwm | SX1262 chip select |
| 38 | 9 | GPIO9LoRa_SCK | strapping | adc · touch · pwm | SX1262 SPI clock |
| 39 | 10 | GPIO10LoRa_MOSI | strapping | adc · touch · pwm | SX1262 SPI MOSI |
| 40 | 11 | GPIO11LoRa_MISO | strapping | adc · touch · pwm | SX1262 SPI MISO |
| 41 | 12 | GPIO12LoRa_RST | strapping | adc · touch · pwm | SX1262 reset |
| 42 | 13 | GPIO13LoRa_BUSY | strapping | adc · touch · pwm | SX1262 BUSY |
| 43 | 14 | GPIO14LoRa_DIO1 | strapping | adc · touch · pwm | SX1262 DIO1 interrupt (the arduino-esp32 variant calls it DIO0) |
| 44 | 17 | GPIO17SDA_OLED | safe | adc · i2c · pwm | OLED I2C data |
| 45 | 18 | GPIO18SCL_OLED | safe | adc · i2c · pwm | OLED I2C clock |
Start with these
9 pins with no boot or system involvementFreely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
19 pins · 16 things to knowGPIO44GPIO43 Used by the CP2102 USB-serial chip onboard hardware
Wired to the CP2102 USB-serial chip on this board. The pin is yours if you give that up, but nothing else can share it.
- GPIO44UART0 RX, wired to the CP2102 TX
- GPIO43UART0 TX, wired to the CP2102 RX
GPIO0 Bootstrapping pin (Chip boot mode selection) Strapping
Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration.
GPIO36 Vext switch: LOW turns the Vext rail (and the OLED) on onboard hardware
Wired to the Vext power switch on this board. The pin is yours if you give that up, but nothing else can share it.
GPIO35 the white user LED through 330R, lit HIGH onboard hardware
Wired to the white user LED on this board. The pin is yours if you give that up, but nothing else can share it.
GPIO47GPIO48 Octal SPI differential clock legs (SPICLK_P/N_DIFF), used only by the 1.8 V octal flash/PSRAM variants Other
Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48.
- GPIO47Octal SPI differential clock positive leg (SPICLK_P_DIFF), used only by the 1.8 V octal flash/PSRAM variants
- GPIO48Octal SPI differential clock negative leg (SPICLK_N_DIFF), used only by the 1.8 V octal flash/PSRAM variants
GPIO21 OLED reset onboard hardware
Wired to the OLED (reset) on this board. The pin is yours if you give that up, but nothing else can share it.
GPIO37 switches the battery-voltage divider onto GPIO1: HIGH to read on V3.2, LOW to read on V3 / V3.1 onboard hardware
Wired to the battery-voltage divider switch on this board. The pin is yours if you give that up, but nothing else can share it.
GPIO46 Bootstrapping pin (used with GPIO0 for boot mode; controls ROM log output) Strapping
Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function.
GPIO45 Bootstrapping pin (selects VDD_SPI flash voltage) Strapping
Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting.
GPIO42 JTAG test mode select pin (MTMS) JTAG
Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB).
GPIO41 JTAG test data in pin (MTDI) JTAG
Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available.
GPIO40 JTAG test data out pin (MTDO) JTAG
Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality.
GPIO39 JTAG test clock (MTCK); IO MUX alternates CLK_OUT3 and SUBSPICS1 (chip select on the alternative SUBSPI memory bus, unused on standard modules) JTAG
Default JTAG TCK - keep it free if you debug over JTAG. It is not a flash or PSRAM line on standard modules: those sit on GPIO26-37.
GPIO1 battery voltage through a 390K / 100K divider (battery = reading x 4.9) while GPIO37 enables it onboard hardware
Wired to the battery-voltage divider on this board. The pin is yours if you give that up, but nothing else can share it.
GPIO3 Bootstrapping pin (controls JTAG signal source) Strapping
Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface.
GPIO17GPIO18 Used by the OLED (I2C) onboard hardware
Wired to the OLED (I2C) on this board. The pin is yours if you give that up, but nothing else can share it.
- GPIO17OLED I2C data
- GPIO18OLED I2C clock
Only if you know the tricks
9 pins · 2 things to knowGPIO20GPIO19 USB OTG differential data pair (D- and D+) USB
By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality.
- GPIO20USB OTG positive differential data line (USB_D+)
- GPIO19USB OTG negative differential data line (USB_D-)
GPIO8GPIO9GPIO10GPIO11GPIO12GPIO13GPIO14 Used by the SX1262 LoRa radio onboard hardware
Wired to the SX1262 LoRa radio on this board, which is soldered down. Driving it from your own code breaks that function.
- GPIO8SX1262 chip select
- GPIO9SX1262 SPI clock
- GPIO10SX1262 SPI MOSI
- GPIO11SX1262 SPI MISO
- GPIO12SX1262 reset
- GPIO13SX1262 BUSY
- GPIO14SX1262 DIO1 interrupt (the arduino-esp32 variant calls it DIO0)
The Heltec WiFi LoRa 32 (V3) pinout brings out 45 pins at a 2.54 mm pitch - 37 usable GPIO alongside the GND, 5V, Ve and 3V3 power rails.
For peripherals, TX/RX on GPIO43 and GPIO44 cover serial logging and flashing.
On the analog side there are 18 ADC-capable pins for sensors and battery monitoring, PWM on every GPIO and 14 capacitive-touch inputs.
If you want zero surprises, GPIO34, GPIO33, GPIO26, GPIO38 and 5 more are free of any such role - the safest first picks. 19 of the exposed pins carry boot-time or system duties on the ESP32-S3 (GPIO44, GPIO43, GPIO0 and 16 more).
Getting started
flash your first firmware in ~2 minutesBoard: Heltec WiFi LoRa 32(V3) Flash Size: 8MB (64Mb) Flash Mode: DIO Partition Scheme: 8M with spiffs (3MB APP/1.5MB SPIFFS) Upload Speed: 921600
// blink the onboard user LED
void setup() {
pinMode(35, OUTPUT);
}
void loop() {
digitalWrite(35, HIGH); delay(500);
digitalWrite(35, LOW); delay(500);
}[env:heltec_wifi_lora_32_V3]
platform = espressif32
board = heltec_wifi_lora_32_V3
framework = arduino
monitor_speed = 115200
upload_speed = 921600heltec_wifi_lora_32_V3 - or type it after board =.esp32:
board: heltec_wifi_lora_32_V3
variant: esp32s3
framework:
type: esp-idf
# blink - GPIO35
output:
- platform: gpio
pin: 35
id: led_out
light:
- platform: binary
name: "LED"
output: led_outheltec_wifi_lora_32_V3 (same ids as PlatformIO).esptool.py --chip esp32s3 --port /dev/ttyACM0 \
--baud 921600 write_flash 0x0 firmware.bin--port = your /dev/tty* (macOS/Linux) or COMx (Windows).Downloads
Free for non-commercial use, credit espboards.dev · License
Board illustration
The bare Heltec WiFi LoRa 32 (V3) board drawn to scale at 50.2 × 25.5 mm, with no pin labels on it. Made for slide decks, wiring diagrams and project write-ups where a photo is too busy. Take the scalable SVG for print or editing, the high-resolution PNG to drop straight in, or the transparent PNG when you need it with no background behind it.
Pinout diagram
Every pin on both sides of the board with its functions, drawn by ESPboards from the ESP32-S3 Series Datasheet v2.2 - the same sheet shown at the top of this page. The PNG is a high-resolution image for screens, the SVG is vector so it stays sharp at any size, and the PDF is laid out to print on A4 or Letter.
Yours to use, share and adapt for non-commercial work, as long as you credit espboards.dev - the full terms and ready-made credit lines are here.
Specifications
ESP32-S3 · 50.2 × 25.5 mm · vs other ESP32 chips →Dimensions
About this board
At its core is the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads.
Expect to pay about $17.90 - less than the ~$29 most ESP32-S3 boards go for.
37 GPIO are broken out - more than most ESP32-S3 boards, so the pin budget is rarely the constraint.
Onboard you'll find an OLED 0.96" 128x64 display, LoRa (SX1262), battery charging via SH1.25 2-pin, status LEDs (User (white), Charge) and Reset/PRG buttons.
- SX1262 LoRa radio on an IPEX 1.0 (u.FL) antenna socket; metal spring antenna for Wi-Fi / BLE
- Sold in two bands: HTIT-WB32LA (863-928 MHz) and HTIT-WB32LAF (470-510 MHz)
- Vext (GPIO36, LOW = on) switches a 3.3 V rail for the OLED and external sensors, 350 mA
- Battery voltage on GPIO1 through a 390K / 100K divider (battery = reading x 4.9), enabled by GPIO37 - drive it HIGH on V3.2 boards, LOW on V3 / V3.1
- Revisions: V3 (2022), V3.1 (2.4 GHz RF moved away from the crystal, USB C-to-C), V3.2 (separate Vext LDO, LGS4056H charger, new battery-read circuit)
- No PSRAM - the ESP32-S3FN8 has 8 MB of in-package flash only
- Native USB (GPIO19/20) is not wired to the USB-C - programming goes through the CP2102
Where to buy
prices are typical street pricesResources
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