Heltec WiFi LoRa 32 V4
ESP32-S3 LoRa board with an SX1262 radio at up to 28 dBm, 0.96 inch OLED, 16MB flash, solar and GNSS connectors, pin-compatible with the V3.
Heltec WiFi LoRa 32 V4 Pinout
36 pins · 2.54 mm pitch
| Pin | GPIO | Labels | Status | Capabilities | Notes |
|---|---|---|---|---|---|
| 1 | - | GND | ground | - | Ground (J2 pin 1) |
| 2 | - | 5V | power | - | 5V input (4.7-6V). Do not use together with USB power |
| 3 | - | Ve | power | - | Switched 3.3V output, on when GPIO36 (Vext_Ctrl) is LOW, max 500mA |
| 4 | - | Ve | power | - | Switched 3.3V output, on when GPIO36 (Vext_Ctrl) is LOW |
| 5 | 44 | RXGPIO44U0RXD | uart | uart · pwm | UART0 RX |
| 6 | 43 | TXGPIO43U0TXD | uart | uart · pwm | UART0 TX |
| 7 | - | RSTCHIP_PU | control | - | Chip enable / reset, wired to the RST button |
| 8 | 0 | 0GPIO0USER_SW | strapping | pwm | PRG button; hold at reset to enter download mode |
| 9 | 36 | 36GPIO36Vext_Ctrl | safe | spi · pwm | Vext_Ctrl on S3R2: LOW enables the Ve outputs (a P-channel switch on the V4.3 schematic; Heltec's datasheet says HIGH). Used by octal PSRAM on the S3R8 variant |
| 10 | 35 | 35GPIO35LED | safe | spi · pwm | White user LED on S3R2. Used by octal PSRAM on the S3R8 variant |
| 11 | 34 | 34GPIO34VGNSS_Ctrl | safe | spi · pwm | GNSS power control on the S3R2 pin map. Used by octal PSRAM on the S3R8 variant |
| 12 | 33 | 33GPIO33 | safe | spi · pwm | Used by octal PSRAM on the S3R8 variant |
| 13 | 47 | 47GPIO47 | strapping | pwm | General-purpose GPIO |
| 14 | 48 | 48GPIO48 | strapping | pwm | General-purpose GPIO |
| 15 | 26 | 26GPIO26SPICS1 | strapping | pwm | SPICS1 |
| 16 | 21 | 21GPIO21OLED_RST | safe | pwm | OLED reset |
| 17 | 20 | 20GPIO20USB_D+U1CTS | uart | adc · pwm | Native USB D+ to the USB-C port. Using it as GPIO breaks USB flashing. ADC2 is unusable with Wi-Fi on |
| 18 | 19 | 19GPIO19USB_D-U1RTS | uart | adc · pwm | Native USB D- to the USB-C port. Using it as GPIO breaks USB flashing. ADC2 is unusable with Wi-Fi on |
| 19 | - | GND | ground | - | Ground (J3 pin 1) |
| 20 | - | 3V3 | power | - | 3.3V supply (in 2.7-3.5V or out, max 500mA) |
| 21 | - | 3V3 | power | - | 3.3V supply |
| 22 | 37 | 37GPIO37ADC_Ctrl | safe | spi · pwm | ADC_Ctrl on S3R2: drive to enable battery voltage reading on GPIO1. Used by octal PSRAM on the S3R8 variant |
| 23 | 46 | 46GPIO46 | strapping | pwm | Free on V4.3 S3R2 (FEM PA control on V4.2; white LED on S3R8) |
| 24 | 45 | 45GPIO45 | strapping | pwm | General-purpose GPIO |
| 25 | 42 | 42GPIO42MTMSGNSS_RST | strapping | pwm | GNSS connector reset (S3R2 pin map). JTAG MTMS |
| 26 | 41 | 41GPIO41MTDIGNSS_PPS | strapping | pwm | GNSS connector PPS. JTAG MTDI |
| 27 | 40 | 40GPIO40MTDOGNSS_Wakeup | strapping | pwm | GNSS connector wake-up on S3R2 (Vext_Ctrl on S3R8). JTAG MTDO |
| 28 | 39 | 39GPIO39MTCKGNSS_TX | strapping | uart · pwm | GNSS connector TX. JTAG MTCK |
| 29 | 38 | 38GPIO38GNSS_RX | uart | uart · spi · pwm | GNSS connector RX |
| 30 | 1 | 1GPIO1ADC1_CH0TOUCH1VBAT_Read | safe | adc · touch · pwm | Battery voltage sense: VBAT = VADC * 490/100 with ADC_Ctrl (GPIO37) HIGH |
| 31 | 2 | 2GPIO2ADC1_CH1TOUCH2FEM_EN | safe | adc · touch · pwm | LoRa FEM chip enable (the PA_CSD net on the V4.3 schematic), used by the radio |
| 32 | 3 | 3GPIO3ADC1_CH2TOUCH3 | strapping | adc · touch · pwm | ADC1, touch |
| 33 | 4 | 4GPIO4ADC1_CH3TOUCH4 | safe | adc · touch · pwm | ADC1, touch |
| 34 | 5 | 5GPIO5ADC1_CH4TOUCH5PA_CTX | safe | adc · touch · pwm | LoRa FEM control (PA_CTX) from hardware V4.3 |
| 35 | 6 | 6GPIO6ADC1_CH5TOUCH6 | safe | adc · touch · pwm | ADC1, touch |
| 36 | 7 | 7GPIO7ADC1_CH6TOUCH7VFEM_Ctrl | safe | adc · touch · pwm | LoRa FEM supply control, used by the radio |
Start with these
13 pins with no boot or system involvementFreely assignable - no strapping, flash, USB or JTAG duties. Ideal first picks for buttons, sensors and LEDs.
Fine - with a little care
12 pins · 11 things to knowRXGPIO44 UART0 receive pin (U0RXD), default serial console RX UART
Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip.
TXGPIO43 UART0 transmit pin (U0TXD), default serial console TX UART
Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0).
0GPIO0 Bootstrapping pin (Chip boot mode selection) Strapping
Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration.
47GPIO4748GPIO48 Octal SPI differential clock legs (SPICLK_P/N_DIFF), used only by the 1.8 V octal flash/PSRAM variants Other
Only the 1.8 V octal parts (ESP32-S3R8V, ESP32-S3R16V) run the differential memory clock here, and on those the pin works at 1.8 V instead of 3.3 V. On the common 3.3 V modules it is a normal GPIO - several devkits drive their RGB LED from GPIO48.
- 47Octal SPI differential clock positive leg (SPICLK_P_DIFF), used only by the 1.8 V octal flash/PSRAM variants
- 48Octal SPI differential clock negative leg (SPICLK_N_DIFF), used only by the 1.8 V octal flash/PSRAM variants
46GPIO46 Bootstrapping pin (used with GPIO0 for boot mode; controls ROM log output) Strapping
Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function.
45GPIO45 Bootstrapping pin (selects VDD_SPI flash voltage) Strapping
Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting.
42GPIO42 JTAG test mode select pin (MTMS) JTAG
Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB).
41GPIO41 JTAG test data in pin (MTDI) JTAG
Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available.
40GPIO40 JTAG test data out pin (MTDO) JTAG
Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality.
39GPIO39 JTAG test clock (MTCK); IO MUX alternates CLK_OUT3 and SUBSPICS1 (chip select on the alternative SUBSPI memory bus, unused on standard modules) JTAG
Default JTAG TCK - keep it free if you debug over JTAG. It is not a flash or PSRAM line on standard modules: those sit on GPIO26-37.
3GPIO3 Bootstrapping pin (controls JTAG signal source) Strapping
Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface.
Only if you know the tricks
3 pins · 2 things to know26GPIO26 SPI0/1 memory-bus chip select 1 (SPICS1) - in-package PSRAM CE# Flash
Part of the SPI0/1 bus that runs the in-package flash and PSRAM, listed by the datasheet as "already allocated or not recommended for use". Modules keep these lines internal, so the pin is not available as GPIO.
20GPIO2019GPIO19 USB OTG differential data pair (D- and D+) USB
By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality.
- 20USB OTG positive differential data line (USB_D+)
- 19USB OTG negative differential data line (USB_D-)
The Heltec WiFi LoRa 32 V4 breaks out 36 pins in total: 28 GPIO for your project, with GND, 5V, Ve and 3V3 handling power.
Peripheral wiring is straightforward: TX/RX on GPIO43 and GPIO44 cover serial logging and flashing.
Beyond plain digital I/O you get 9 ADC-capable pins for sensors and battery monitoring, PWM on every GPIO and 7 capacitive-touch inputs.
12 of the exposed pins carry boot-time or system duties on the ESP32-S3 (RX, TX, 0 and 9 more) - check the guidance above before wiring anything to them. 36, 35, 34, 33 and 9 more are free of any such role - the safest first picks.
Getting started
flash your first firmware in ~2 minutesBoard: ESP32S3 Dev Module USB CDC On Boot: Enabled Flash Size: 16MB (128Mb) PSRAM: QSPI PSRAM Partition Scheme: 16M Flash (3MB APP/9.9MB FATFS) Upload Speed: 921600
// blink the onboard user LED
void setup() {
pinMode(35, OUTPUT);
}
void loop() {
digitalWrite(35, HIGH); delay(500);
digitalWrite(35, LOW); delay(500);
}[env:heltec-wifi-lora-32-v4]
platform = espressif32
board = esp32-s3-devkitc-1
framework = arduino
monitor_speed = 115200
upload_speed = 921600
board_build.arduino.memory_type = qio_qspi
build_flags = -DBOARD_HAS_PSRAMesp32-s3-devkitc-1 - or type it after board =.esp32:
board: esp32-s3-devkitc-1
variant: esp32s3
framework:
type: esp-idf
psram:
mode: quad
speed: 80MHz
# blink - GPIO35
output:
- platform: gpio
pin: 35
id: led_out
light:
- platform: binary
name: "LED"
output: led_outesp32-s3-devkitc-1 (same ids as PlatformIO).esptool.py --chip esp32s3 --port /dev/ttyACM0 \
--baud 921600 write_flash 0x0 firmware.bin--port = your /dev/tty* (macOS/Linux) or COMx (Windows).Good to know
board-specific quirks worth 60 secondsThe V4 is sold with an ESP32-S3R2 (2MB PSRAM) or an ESP32-S3R8 (8MB octal PSRAM), and the two use different pin maps. On the R8 the octal PSRAM takes GPIO33-GPIO37. Vext control moves from GPIO36 to GPIO40, the white LED from GPIO35 to GPIO46, and GNSS power control moves to GPIO42. The pin table on this page follows the S3R2 map. Code written for one variant can switch the wrong pins on the other. Check…
The V4 is sold with an ESP32-S3R2 (2MB PSRAM) or an ESP32-S3R8 (8MB octal PSRAM), and the two use different pin maps. On the R8 the octal PSRAM takes GPIO33-GPIO37. Vext control moves from GPIO36 to GPIO40, the white LED from GPIO35 to GPIO46, and GNSS power control moves to GPIO42. The pin table on this page follows the S3R2 map.
Code written for one variant can switch the wrong pins on the other. Check which chip your board has before you drive Vext, the LED or the GNSS pins.
Several header GPIOs are already in use on the board. GPIO2 (FEM_EN), GPIO7 (FEM supply) and GPIO5 (PA control) drive the LoRa front end. GPIO1 reads battery voltage when GPIO37 (ADC_Ctrl) is driven, and GPIO38-GPIO42 go to the GNSS connector. The SX1262 itself uses GPIO8-GPIO14 internally, and the OLED uses I2C on GPIO17/GPIO18 with reset on GPIO21. Hardware V4.3 moved the LoRa front end to a KCT8103L FEM,…
Several header GPIOs are already in use on the board. GPIO2 (FEM_EN), GPIO7 (FEM supply) and GPIO5 (PA control) drive the LoRa front end. GPIO1 reads battery voltage when GPIO37 (ADC_Ctrl) is driven, and GPIO38-GPIO42 go to the GNSS connector. The SX1262 itself uses GPIO8-GPIO14 internally, and the OLED uses I2C on GPIO17/GPIO18 with reset on GPIO21.
Hardware V4.3 moved the LoRa front end to a KCT8103L FEM, which made GPIO5 the PA control pin and freed GPIO46. V4.2 boards used a GC1109 PA that is controlled differently, so check the board revision before you use either pin.
Downloads
Free for non-commercial use, credit espboards.dev · License
Board illustration
The bare Heltec WiFi LoRa 32 V4 board drawn to scale at 51.69 × 25.4 mm, with no pin labels on it. Made for slide decks, wiring diagrams and project write-ups where a photo is too busy. Take the scalable SVG for print or editing, the high-resolution PNG to drop straight in, or the transparent PNG when you need it with no background behind it.
Pinout diagram
Every pin on both sides of the board with its functions, drawn by ESPboards from the ESP32-S3 Series Datasheet v2.2 - the same sheet shown at the top of this page. The PNG is a high-resolution image for screens, the SVG is vector so it stays sharp at any size, and the PDF is laid out to print on A4 or Letter.
Yours to use, share and adapt for non-commercial work, as long as you credit espboards.dev - the full terms and ready-made credit lines are here.
Specifications
ESP32-S3 · 51.69 × 25.4 mm · vs other ESP32 chips →Dimensions
About this board
Inside sits the ESP32-S3 - a dual-core Xtensa with vector extensions suited to AI workloads.
At $19.90 it's cheaper than most ESP32-S3 boards, which usually run around $29.
With 28 GPIO broken out, you get more pins to play with than most ESP32-S3 boards offer.
Around the module: 2MB PSRAM, an OLED 0.96" 128x64 display, LoRa (SX1262), battery charging via SH1.25-2P, status LEDs (White, Orange) and Reset/PRG (user / boot) buttons.
It flashes over native USB - no serial-converter driver needed, which isn't a given among ESP32-S3 boards.
- LoRa TX power up to 28 +/- 1 dBm (863-928 MHz high-power version); low-power version 21 dBm
- SH1.25-2P solar panel input (4.7-6V)
- SH1.25-8P GNSS module connector
- IPEX 1.0 LoRa antenna connector; 2.4 GHz FPC antenna built into the screen bracket
- Also sold as ESP32-S3R8 with 8MB PSRAM, and without the OLED
- Using the onboard IPEX 2.4G connector instead of the FPC antenna needs a 0 ohm resistor moved first
- Power from USB or the 5V pin, never both at once; a battery and a solar panel can be connected alongside either
Where to buy
prices are typical street pricesResources
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