XIAO ESP32S3 Plus Development Board
Code name: XIAO_ESP32S3_PLUS
XIAO ESP32S3 Plus development board is based on esp32s3 microcontroller and uses xtensa architecture. This board has a maximum CPU frequency of 240 MHz and a flash size of 16MB.
About XIAO ESP32S3 Plus
The XIAO ESP32S3 Plus is a high-performance development board based on the ESP32-S3 dual-core processor with enhanced features. It supports WiFi 4 and Bluetooth 5 (LE), making it ideal for IoT, AI, and embedded applications. 📡
With a compact yet powerful design, it includes a USB-C port for fast programming and power, and features additional onboard peripherals such as an integrated accelerometer and external memory support. ⚡
The XIAO ESP32S3 Plus supports multiple communication interfaces, including UART, I2C, SPI, and ADC, making it a great choice for advanced embedded applications.
Where to Buy
Starting from
20$ per unit
Prices are subject to change. We earn from qualifying purchases as an Amazon Associate.
Technical Specifications
🔌 USB
🛰️ Connectivity
🧠 Microcontroller
✨ Features
- Dual-core Xtensa LX7 processor with enhanced AI capabilities
- Integrated accelerometer and external memory support
- Supports WiFi 4 and Bluetooth 5 (LE)
- Ultra-small size (21x17.5 mm)
- 18 digital IO pins
- 18 external interrupt pins
- 9 analog input pins
- 18 PWM pins
XIAO ESP32S3 Plus Pinout
The XIAO ESP32S3 Plus pinout is designed for expanded functionality and includes additional peripheral connections. It features key power pins like 5V, 3.3V, and GND for stable power delivery.
It supports multiple communication protocols, including UART (RX and TX), I2C (SDA and SCL), and SPI (SCK, MISO, MOSI, and SS).
Analog input pins labeled A0 to A3 enable sensor integration, while additional GPIOs provide further expandability.
✅ Safe Pins to Use
For general GPIO usage, these are the safest and most flexible choices:
Why Are These Pins Safe?
- Not involved in bootstrapping → No impact on device boot mode or system startup
- Not linked to flash memory or PSRAM → Won't interfere with storage or memory access
- Not dedicated to USB or JTAG → Free for general use without affecting debugging
- No special hardware connections → Freely assignable without internal conflicts
⚠️ Pins to Avoid or Use with Caution
Some pins are reserved for critical functions like bootstrapping, JTAG debugging, USB communication, and flash memory operations. Misusing these pins may lead to boot failures, programming issues, USB conflicts, or disruptions in flash storage.
Critical Pin Categories:
- 🛠️ Strapping Pins: Control boot behavior and flash voltage selection
- 🔗 JTAG Debugging Pins: Required for low-level debugging
- 🔌 USB Communication Pins: Used for USB Serial/JTAG communication
- ⚡ Flash Memory & SPI Pins: Connected to SPI flash memory and PSRAM
- 📡 UART Serial Communication Pins: Used for debugging and firmware uploads
| PIN | Label | Reason | Function |
|---|---|---|---|
| IO3 | GPIO3 | Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface. | 🛠️ Strapping |
| IO9 | FSPIHD | Connected to external flash (data/hold signal) on most modules. Not recommended for use as GPIO, since it must remain dedicated to flash communication. | ⚡ Flash |
| IO10 | FSPICS0 | Used to select the external flash chip. It is required for flash access and cannot be repurposed without losing flash connectivity | ⚡ Flash |
| IO20 | USB_D+ | By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality. | 🔌 USB |
XIAO ESP32S3 Plus Pin Mappings
This development board provides 18 digital IO pins, out of which 18 can be used as external interrupt pins , 9 as analog input pins and 18 pins have Pulse-Width Modulation (PWM) .
| Pin | Function | ESP Pin | Input/Output | Description |
|---|---|---|---|---|
| 1 | 5V | 5V | POWER INPUT | 5V power input |
| 2 | GND | GND | GROUND | Ground connection |
| 3 | 3V3 | 3.3V | POWER OUTPUT | 3.3V power output |
| 4 | IO2 | A0 | BIDIRECTIONAL | GPIO, ADC |
| 5 | IO3 | A1 | BIDIRECTIONAL | GPIO, ADC |
| 6 | IO4 | A2 | BIDIRECTIONAL | GPIO, ADC |
| 7 | IO5 | A3 | BIDIRECTIONAL | GPIO, ADC |
| 8 | IO6 | SDA | BIDIRECTIONAL | GPIO, I2C Data |
| 9 | IO7 | SCL | BIDIRECTIONAL | GPIO, I2C Clock |
| 10 | IO8 | SCK | BIDIRECTIONAL | GPIO, SPI Clock |
| 11 | IO9 | MISO | BIDIRECTIONAL | GPIO, SPI Data |
| 12 | IO10 | MOSI | BIDIRECTIONAL | GPIO, SPI Data |
| 13 | IO20 | RX | BIDIRECTIONAL | GPIO, UART Receive |
| 14 | IO21 | TX | BIDIRECTIONAL | GPIO, UART Transmit |
Default Tools
| Bootloader tool | esptool_py |
| Uploader tool | esptool_py |
| Network uploader tool | esp_ota |
| Bootloader address | 0x0 |
| Flash mode | qio |
| Boot mode | qio |
| Maximum upload size | 8192 Kb (8388608 B) |
| Maximum data size | 320 Kb (327680 B) |
The XIAO ESP32S3 Plus development board by default uses esptool_py uploader tool, esp_ota network uploader tool for Over-the-air (OTA) uploads and esptool_py bootloader tool. The bootloader starts at address "0x0". Flash mode and boot mode for XIAO ESP32S3 Plus development board by default is qio and qio respectively.
