ESP32 Boards/ESP32-C5

ESP32-C5 Development Boards

The ESP32-C5 is Espressif's first dual-band Wi-Fi 6 chip, adding a 5 GHz radio alongside the usual 2.4 GHz band. It pairs a single-core 32-bit RISC-V CPU running up to 240 MHz with Bluetooth 5 (LE) and an 802.15.4 radio for Thread and Zigbee.

In practice it is a 5 GHz-capable sibling of the ESP32-C6, well suited to less congested 5 GHz networks, Matter devices, and higher-throughput IoT links. After a long pre-release period it now ships on development boards such as the ESP32-C5-DevKitC-1 and Seeed XIAO ESP32-C5, with support in ESP-IDF (v5.5+).

Single-core
RISC-V cores
240 MHz
Max clock
384 KB
SRAM
0
Boards

Specifications

Datasheet ↗

Compute

CPURISC-V single-core 32-bit
Clock240 MHz
SRAM384 KB
Operating temp-40 to 85 °C

Connectivity

Wi-Fi802.11 ax b/g/n (2.4 GHz / 5 GHz)
Bluetooth5.0
BLE5.0
Thread / Zigbee802.15.4 (Thread / Zigbee)

Peripherals

PWM6

Strapping & reserved pins

7 pins to know

Some pins are reserved for boot strapping, JTAG, USB and flash - misusing them can cause boot failures or programming issues. The category colours below match the table.

Strapping boot mode & flash voltage JTAG low-level debugging USB native USB Serial/JTAG Flash / SPI flash & PSRAM lines UART debug & firmware upload
PinLabelWhy avoidCategory
GPIO28GPIO28Must stay HIGH at reset for normal SPI boot; pulling it LOW forces joint download (flashing) mode. Free to use as GPIO after reset.Strapping
GPIO27GPIO27 / VDD_SPIHeld HIGH at reset for normal boot; it also powers external flash by default, so driving it can change the boot mode / ROM-log output or cut flash power.Strapping
GPIO26GPIO26Sampled at reset for boot mode; avoid holding it at a fixed level during boot unless intentionally selecting download mode. Free after reset.Strapping
GPIO25GPIO25Latched at reset to set SDIO clock-edge behaviour; avoid driving at boot unless configuring SDIO timing. Free as GPIO after reset.Strapping
GPIO7GPIO7 (JTAG_SEL)Must be driven to a defined level by external circuitry at reset (never left floating) to select the JTAG source; free as GPIO afterwards.JTAG
MTDIMTDIPart of the JTAG interface and sampled at reset; avoid using as GPIO when JTAG debugging or SDIO is in use.JTAG

ESP32-C5 modules & revisions

3 variants

ESP32-C5 boards

0 boards

No ESP32-C5 boards documented yet - browse all ESP32 boards →