ESP32-H2 Development Boards

2 boards · Single-core RISC-V · 96 MHz

The ESP32-H2 is built for Thread and Zigbee applications with support for 802.15.4 mesh networking and Bluetooth 5 LE. Unlike other ESP chips, it omits Wi-Fi, focusing on ultra-low power and long battery life.

It uses a single-core RISC-V CPU and integrates advanced security features. It's tailored for smart lighting, sensor hubs, and low-power mesh nodes in the Matter ecosystem.

Compare all ESP32 chips → Datasheet ↗

Single-core

RISC-V cores

96 MHz

Max clock

320 KB

SRAM

Boards

Specifications

Datasheet ↗

Compute

CPURISC-V single-core 32-bit

Clock96 MHz

SRAM320 KB

Operating temp-40 to 85 °C

Connectivity

Wi-FiNone

Bluetooth5.0

BLE5.0

Peripherals

SPI1

I²C2

I²S1

RMT4 Channels

UART2

PWM6

Strapping & reserved pins

13 pins to know

Some pins are reserved for boot strapping, JTAG, USB and flash - misusing them can cause boot failures or programming issues. The category colours below match the table.

Strapping boot mode & flash voltage JTAG low-level debugging USB native USB Serial/JTAG Flash / SPI flash & PSRAM lines PSRAM memory line only on PSRAM-equipped modules UART debug & firmware upload

Pin	Label	Why avoid	Category
IO0	GPIO0 (FSPIQ)	IO MUX pin of the general-purpose SPI2 (FSPI) bus. The H2 runs its in-package flash on GPIO15-20, which the QFN32 package does not route out, so this pin is free unless your board wires an SPI peripheral to FSPI.	Other
IO1	GPIO1 (FSPICS0)	IO MUX pin of the general-purpose SPI2 (FSPI) bus. The H2 runs its in-package flash on GPIO15-20, which the QFN32 package does not route out, so this pin is free unless your board wires an SPI peripheral to FSPI.	Other
IO2	MTMS	Default JTAG TMS line - using it as GPIO disables external JTAG debugging. It is not a flash pin: the H2 keeps its in-package flash on GPIO15-20, which the QFN32 package does not route out.	JTAG
IO3	MTDO	Default JTAG TDO line - using it as GPIO disables external JTAG debugging. It is not a flash pin: the H2 keeps its in-package flash on GPIO15-20, which the QFN32 package does not route out.	JTAG
IO4	MTCK	Default JTAG TCK line - using it as GPIO disables external JTAG debugging. It is not a flash pin: the H2 keeps its in-package flash on GPIO15-20, which the QFN32 package does not route out.	JTAG
IO5	MTDI	Default JTAG TDI line - using it as GPIO disables external JTAG debugging. It is not a flash pin: the H2 keeps its in-package flash on GPIO15-20, which the QFN32 package does not route out.	JTAG
IO8	GPIO8	Must be held at the proper logic level on reset to select the correct boot mode and enable/disable bootloader log output.	Strapping
IO9	GPIO9	Must be pulled high on reset for normal SPI flash boot (pulling it low while GPIO8 is high forces the chip into download/programming mode).	Strapping
IO23	U0RXD	Often used for the serial console and bootloader input; repurposing it may conflict with UART communication for programming or debugging.	UART
IO24	U0TXD	Often used for boot log output and serial debugging; repurposing it can disable serial output of boot messages and interfere with console debugging.	UART
IO25	GPIO25	Used during boot to determine the JTAG interface source; this pin has no internal pull-up/down, so it must not be left floating (an external resistor drives it high/low to avoid unintended JTAG mode selection).	Strapping
IO26	USB_D-	By default, this pin is connected to the chip's internal USB Serial/JTAG peripheral; using it as a general-purpose IO requires disabling or reconfiguring that USB interface.	USB
IO27	USB_D+	By default, this pin is connected to the internal USB Serial/JTAG controller; using it as a general-purpose IO would disable the USB functionality used for debugging/programming.	USB