esp32h2 Development Boards

The list of esp32h2 development boards, complete with pinouts, technical specifications, datasheets and more.

The ESP32-H2 is built for Thread and Zigbee applications with support for 802.15.4 mesh networking and Bluetooth 5 LE. Unlike other ESP chips, it omits Wi-Fi, focusing on ultra-low power and long battery life.

It uses a single-core RISC-V CPU and integrates advanced security features. It's tailored for smart lighting, sensor hubs, and low-power mesh nodes in the Matter ecosystem.

Technical Specifications

🧠 Microcontroller

Microcontroller RISC-V single-core 32-bit

Frequency Up to 96 MHz

📡 Connectivity

WiFi -

Bluetooth 5.0

BLE 5.0

🔌 Interfaces

SPI 2

I2C 1

📄 View Datasheet

Strapping Pins

Some pins are reserved for critical functions like bootstrapping, JTAG debugging, USB communication, and flash memory operations. Misusing these pins may lead to boot failures, programming issues, USB conflicts, or disruptions in flash storage.

Critical Pin Categories:

🛠️ Strapping Pins: Control boot behavior and flash voltage selection
🔗 JTAG Debugging Pins: Required for low-level debugging
🔌 USB Communication Pins: Used for USB Serial/JTAG communication
⚡ Flash Memory & SPI Pins: Connected to SPI flash memory and PSRAM
📡 UART Serial Communication Pins: Used for debugging and firmware uploads

PIN	Label	Reason	Function
IO0	GPIO0	Connected to the external (or in-package) flash memory as a data line; cannot be repurposed without interfering with program storage.	⚡ Flash
IO1	GPIO1	Used to select the SPI flash chip (not brought out on modules with in-package flash); needed for flash access, so it should not be used as a general IO.	⚡ Flash
IO2	MTMS	Serves as the flash memory’s write-protect pin and the JTAG TMS line; using it as GPIO can disrupt flash operation or JTAG debugging.	⚡ Flash
IO3	MTDO	Serves as the flash HOLD (D3) line and the JTAG TDO output; repurposing it can interfere with flash reads/writes or JTAG debugging.	⚡ Flash
IO4	MTCK	Acts as the SPI flash clock line and the JTAG clock; cannot be used as GPIO without halting flash operation or debug capability.	⚡ Flash
IO5	MTDI	Functions as the flash data input (D0) line and JTAG TDI input; using it as GPIO will interfere with the flash data bus and JTAG functionality.	⚡ Flash
IO8	GPIO8	Must be held at the proper logic level on reset to select the correct boot mode and enable/disable bootloader log output.	🛠️ Strapping
IO9	GPIO9	Must be pulled high on reset for normal SPI flash boot (pulling it low while GPIO8 is high forces the chip into download/programming mode).	🛠️ Strapping
IO23	U0RXD	Often used for the serial console and bootloader input; repurposing it may conflict with UART communication for programming or debugging.	📡 UART
IO24	U0TXD	Often used for boot log output and serial debugging; repurposing it can disable serial output of boot messages and interfere with console debugging.	📡 UART
IO25	GPIO25	Used during boot to determine the JTAG interface source; this pin has no internal pull-up/down, so it must not be left floating (an external resistor drives it high/low to avoid unintended JTAG mode selection).	🛠️ Strapping
IO26	USB_D-	By default, this pin is connected to the chip’s internal USB Serial/JTAG peripheral; using it as a general-purpose IO requires disabling or reconfiguring that USB interface.	🔌 USB
IO27	USB_D+	By default, this pin is connected to the internal USB Serial/JTAG controller; using it as a general-purpose IO would disable the USB functionality used for debugging/programming.	🔌 USB