ESP32-C6 Development Boards

8 boards · Single-core RISC-V · 160 MHz

The ESP32-C6 introduces Wi-Fi 6 (802.11ax) and BLE 5.3 for next-gen IoT. It’s also the first ESP chip to support Thread and Zigbee (802.15.4), making it ideal for Matter-compatible smart home devices.

Built on a RISC-V core, the C6 supports secure OTA, IPv6, and robust RF performance. It’s great for low-latency, low-power mesh networks, and future-proof IoT ecosystems.

Compare all ESP32 chips → Datasheet ↗

Single-core

RISC-V cores

160 MHz

Max clock

512 KB

SRAM

Boards

Specifications

Datasheet ↗

Compute

CPURISC-V single-core 32-bit

Clock160 MHz

SRAM512 KB

Operating temp-40 to 85 °C

Connectivity

Wi-Fi802.11 ax b/g/n (2.4 GHz)

Bluetooth5.3

BLE5.3

Thread / Zigbee802.15.4 (Thread / Zigbee)

Peripherals

ADCOne 12-bit, 7 Channels

SPI1

I²C1 +1 LP

I²S1

RMT4 Channels

UART2 +1 LP

PWM6

Strapping & reserved pins

18 pins to know

Some pins are reserved for boot strapping, JTAG, USB and flash - misusing them can cause boot failures or programming issues. The category colours below match the table.

Strapping boot mode & flash voltage JTAG low-level debugging USB native USB Serial/JTAG Flash / SPI flash & PSRAM lines PSRAM memory line only on PSRAM-equipped modules UART debug & firmware upload

Pin	Label	Why avoid	Category
IO4	MTMS	Used during boot; required for JTAG debugging; flash data in internal-flash models.	Strapping
IO5	MTDI	Used during boot; required for JTAG debugging; flash data in internal-flash models.	Strapping
IO6	MTCK	Required for JTAG debugging; connected to flash clock in internal-flash models.	JTAG
IO7	MTDO	Required for JTAG debugging; connected to flash data in internal-flash models.	JTAG
IO8	GPIO8	Determines boot mode; pulling low at reset can prevent normal boot.	Strapping
IO9	GPIO9	Pulling low on reset forces the ESP32-C6 into download mode instead of normal boot.	Strapping
IO12	USB_D-	Dedicated to USB communication; avoid if using USB functionality.	USB
IO13	USB_D+	Dedicated to USB communication; avoid if using USB functionality.	USB
IO15	JTAG_SEL	Controls JTAG input source at boot; avoid altering its state.	JTAG
IO16	U0TXD	Default UART0 transmit pin; using it may interfere with serial console or programming.	UART
IO17	U0RXD	Default UART0 receive pin; using it may interfere with serial console or programming.	UART
IO24	SPICS0	One of the SPI0/1 lines the datasheet recommends for the off-package flash (GPIO24, 25, 26, 28, 29, 30). Modules wire their flash here, so using it as GPIO breaks program storage.	Flash
IO25	SPIQ	One of the SPI0/1 lines the datasheet recommends for the off-package flash (GPIO24, 25, 26, 28, 29, 30). Modules wire their flash here, so using it as GPIO breaks program storage.	Flash
IO26	SPIWP	One of the SPI0/1 lines the datasheet recommends for the off-package flash (GPIO24, 25, 26, 28, 29, 30). Modules wire their flash here, so using it as GPIO breaks program storage.	Flash
IO27	VDD_SPI	The datasheet calls GPIO27 "the power supply pin for off-package flash by default", reconfigurable as a GPIO only if the flash is powered from an external supply. Modules do not break it out.	Flash
IO28	SPIHD	One of the SPI0/1 lines the datasheet recommends for the off-package flash (GPIO24, 25, 26, 28, 29, 30). Modules wire their flash here, so using it as GPIO breaks program storage.	Flash
IO29	SPICLK	One of the SPI0/1 lines the datasheet recommends for the off-package flash (GPIO24, 25, 26, 28, 29, 30). Modules wire their flash here, so using it as GPIO breaks program storage.	Flash
IO30	SPID	One of the SPI0/1 lines the datasheet recommends for the off-package flash (GPIO24, 25, 26, 28, 29, 30). Modules wire their flash here, so using it as GPIO breaks program storage.	Flash