ESP32-C3 Development Boards
The ESP32-C3 is a RISC-V-based Wi-Fi + BLE SoC with a focus on low power, cost-efficiency, and enhanced security. It is ideal for smart plugs, BLE beacons, and battery-powered IoT nodes.
Features include BLE 5.0, Wi-Fi 4, and hardware security (secure boot, flash encryption). It's fully supported in the Arduino IDE, ESP-IDF, and Rust.
Single-core
RISC-V cores
160 MHz
Max clock
400 KB
SRAM
25
Boards
Specifications
Datasheet ↗Compute
CPURISC-V single-core 32-bit
Clock160 MHz
SRAM400 KB
Operating temp-40 to 85 °C
Connectivity
Wi-Fi802.11 b/g/n (2.4 GHz)
Bluetooth5.0
BLE5.0
Peripherals
ADCTwo 12-bit, 6 Channels
SPI3
I²C1
I²S1
RMT4 Channels
UART2
PWM6
Strapping & reserved pins
18 pins to knowSome pins are reserved for boot strapping, JTAG, USB and flash - misusing them can cause boot failures or programming issues. The category colours below match the table.
Strapping boot mode & flash voltage JTAG low-level debugging USB native USB Serial/JTAG Flash / SPI flash & PSRAM lines UART debug & firmware upload
| Pin | Label | Why avoid | Category |
|---|---|---|---|
| IO2 | GPIO2 | Must be held high during boot (if low on reset, normal flash boot may fail) | Strapping |
| IO4 | MTMS | Used during boot; JTAG TMS for debugging; acts as Quad-SPI flash IO (hold data line) in internal-flash variants | JTAG |
| IO5 | MTDI | Used during boot; JTAG TDI for debugging; acts as Quad-SPI flash IO (write-protect data line) in internal-flash variants | JTAG |
| IO6 | MTCK | Used during boot; JTAG TCK for debugging; provides flash clock in internal-flash variants | JTAG |
| IO7 | MTDO | Used during boot; JTAG TDO for debugging; acts as Quad-SPI flash IO (data line) in internal-flash variants | JTAG |
| IO8 | GPIO8 | Must be held high during reset (if low, UART flashing/boot may not work) | Strapping |
| IO9 | GPIO9 | Controls boot mode on reset (HIGH for normal flash boot, LOW enters serial download mode) | Strapping |
| IO11 | VDD_SPI | By default powers the SPI flash; only configurable as GPIO if the flash is powered externally (not recommended otherwise) | Flash |
| IO12 | SPIHD | Connected to flash HOLD#; not recommended for other use as it’s reserved for flash communication | Flash |
| IO13 | SPIWP | Connected to flash WP#; not recommended for other use (used to interface with SPI flash) | Flash |
| IO14 | SPICS0 | Dedicated chip-select for SPI flash memory; cannot be repurposed for general I/O | Flash |
| IO15 | SPICLK | Dedicated clock line for SPI flash; cannot be used as general GPIO without interfering with flash | Flash |
| IO16 | SPID | Used for SPI flash data transfer (data-out from flash); not available for other functions | Flash |
| IO17 | SPIQ | Used for SPI flash data transfer (data-in to flash); not available for other functions | Flash |
| IO18 | USB_D- | By default connected to on-chip USB Serial/JTAG controller; to use as GPIO it must be reconfigured from its USB function | USB |
| IO19 | USB_D+ | By default connected to on-chip USB Serial/JTAG controller; not available for GPIO use unless USB functionality is disabled or remapped | USB |
| IO20 | U0RXD | Used as UART0 receive (console/bootloader); repurposing may disable serial programming and debug logs | UART |
| IO21 | U0TXD | Used as UART0 transmit (console/bootloader); repurposing may disable serial console output and printing | UART |
ESP32-C3 modules & revisions
4 variants
ESP32-C3 boards
25 boards
