esp32s3 Development Boards

The list of esp32s3 development boards, complete with pinouts, technical specifications, datasheets and more.

The ESP32-S3 combines Wi-Fi + BLE with AI acceleration via its vector instructions. It is perfect for projects requiring face recognition, gesture detection, or machine learning inference at the edge.

It features a dual-core processor, USB OTG, and enhanced GPIOs supporting 8-bit parallel LCDs and camera interfaces. It’s supported by both ESP-IDF and Arduino, ideal for AIoT development.

Technical Specifications

🧠 Microcontroller

Microcontroller Xtensa dual-core 32-bit LX7

Frequency Up to 240 MHz

📡 Connectivity

WiFi 802.11 b/g/n (2.4 GHz)

Bluetooth 5.0

BLE 5.0

🔌 Interfaces

Analog-Digital Converter (ADC) Two 12-bit, 20 Channels

SPI 4

I2C 2

I2S 2

RMT 8 Channels

Touch Sensor Pins 14

📄 View Datasheet

Strapping Pins

Some pins are reserved for critical functions like bootstrapping, JTAG debugging, USB communication, and flash memory operations. Misusing these pins may lead to boot failures, programming issues, USB conflicts, or disruptions in flash storage.

Critical Pin Categories:

🛠️ Strapping Pins: Control boot behavior and flash voltage selection
🔗 JTAG Debugging Pins: Required for low-level debugging
🔌 USB Communication Pins: Used for USB Serial/JTAG communication
⚡ Flash Memory & SPI Pins: Connected to SPI flash memory and PSRAM
📡 UART Serial Communication Pins: Used for debugging and firmware uploads

PIN	Label	Reason	Function
IO0	GPIO0	Must be pulled high (default) or low (to enter UART download mode) at reset. Using it for other functions can interfere with boot mode configuration.	🛠️ Strapping
IO3	GPIO3	Sampled at reset to select JTAG interface (USB Serial/JTAG controller vs. external pins). Improper use can disable external JTAG or alter debug interface.	🛠️ Strapping
IO9	FSPIHD	Connected to external flash (data/hold signal) on most modules. Not recommended for use as GPIO, since it must remain dedicated to flash communication.	⚡ Flash
IO10	FSPICS0	Used to select the external flash chip. It is required for flash access and cannot be repurposed without losing flash connectivity	⚡ Flash
IO11	FSPID	Used as a data line for flash (and in-package PSRAM). It should not be used as GPIO when the flash/PSRAM is in use.	⚡ Flash
IO12	FSPICLK	Drives the flash (and PSRAM) clock. This critical signal must be reserved for memory and not used as general GPIO.	⚡ Flash
IO13	FSPIQ	Used as a data line for flash/PSRAM transfers. Not available for other uses when flash/PSRAM is connected.	⚡ Flash
IO14	FSPIWP	Connected to external flash (data/write-protect signal). Not recommended as GPIO because it’s reserved for flash operations.	⚡ Flash
IO19	USB_D-	By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality.	🔌 USB
IO20	USB_D+	By default connected to the on-chip USB Serial/JTAG controller. Using it as general GPIO without reconfiguring IO MUX will interfere with USB functionality.	🔌 USB
IO33	FSPIHD	On chips/modules with integrated flash, this IO is wired to the flash hold pin internally. It cannot be reassigned to GPIO without breaking flash access.	⚡ Flash
IO34	FSPICS0	Wired to the chip select of the internal flash in flash-equipped variants. It must remain low during flash operation, so it’s not available for other use.	⚡ Flash
IO35	FSPID / PSRAM_D0	In modules with octal PSRAM, this pin is connected to the PSRAM data line. It is reserved for memory interface and not free for general GPIO when flash/PSRAM is present.	⚡ Flash
IO36	FSPICLK / PSRAM_CLK	In modules with octal PSRAM, this pin drives the PSRAM clock. It must be dedicated to the memory interface, not used as a regular GPIO when that interface is in use.	⚡ Flash
IO37	FSPIQ / PSRAM_DQS	In modules with octal PSRAM, this pin is connected to the PSRAM’s DQS signal. It cannot be repurposed without disrupting the PSRAM/flash communication.	⚡ Flash
IO38	FSPIWP	On flash-equipped chips, this pin is tied to the flash’s WP# (or D3) line. It should be avoided for other use, as it’s needed for flash operations.	⚡ Flash
IO39	MTCK (GPIO39)	Default JTAG debugging TCK pin. If JTAG is needed, this pin must be free; it may also be used internally for PSRAM chip select on certain modules, so avoid repurposing it.	🪛 Other
IO40	MTDO (GPIO40)	Default JTAG TDO output for debugging. Using it as GPIO will interfere with JTAG debugging functionality.	🪛 Other
IO41	MTDI (GPIO41)	Default JTAG TDI input for debugging. Should be reserved for JTAG or left unused if JTAG is to remain available.	🪛 Other
IO42	MTMS (GPIO42)	Default JTAG TMS signal for debugging. Using this pin for other purposes will disable the JTAG interface (unless JTAG is rerouted to USB).	🪛 Other
IO43	U0TXD (GPIO43)	Used for bootloader output and UART console logs. If repurposed, you will lose the default serial output (and programming via UART0).	🪛 Other
IO44	U0RXD (GPIO44)	Used for bootloader input (download mode via serial). If repurposed, you cannot use the default UART0 download mode for programming the chip.	🪛 Other
IO45	GPIO45	Determines flash/PSRAM power voltage (3.3 V vs 1.8 V) at boot. Must match hardware configuration; using as GPIO can upset flash supply setting.	🛠️ Strapping
IO46	GPIO46	Must be at a defined level during reset (with GPIO0) to select normal or download boot and UART/USB print mode. This pin is input-only (no output drive), so it should be left for its intended strapping function.	🛠️ Strapping
IO47	SPICLK_P	Used only on variants with Octal SPI interface (e.g. ESP32-S3R16V) as part of the differential clock pair. On such chips it operates at 1.8 V and is reserved for the high-speed octal SPI clock, not for general GPIO use.	⚡ Flash
IO48	SPICLK_N	Used only on variants with Octal SPI interface, as the negative leg of the differential clock&. On such chips it operates at 1.8 V; it should be avoided for GPIO to prevent conflicts with the octal flash/PSRAM clock.	⚡ Flash